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參數(shù)資料
| 型號： | TSB43AA82A1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| 中文描述： | 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器） |
| 文件頁數(shù)： | 123/146頁 |
| 文件大小： | 597K |
| 代理商： | TSB43AA82A1 |
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111
11 PHY
11.1 Description
The physical interface portion of the TSB43AA82A provides the digital and analog transceiver functions needed to
implement a two-port node in a cable-based IEEE 1394 network. The cable ports incorporate two differential line
transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection
status, for initialization and arbitration, and for packet reception and transmission. The TSB43AA82A requires only
an external 24.576-MHz crystal as a reference. An external clock can be provided instead of a crystal. An internal
oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal.
This reference signal is internally divided to provide the clock signals used to control transmission of the outbound
encoded strobe and data information. A 49.152-MHz clock signal is supplied to the associated link layer controller
(LLC, internal to iSphynxII) for synchronization of the two portions and is used for resynchronization of the received
data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.
During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers
for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe
information is received on the TPB cable pair(s). The received data-strobe information is decoded to recover the
receive clock signal and the serial data bits.
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel also monitors the incoming cable common-mode voltage. The common-mode
voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel
monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied
twisted-pair bias voltage.
The TSB43AA82A provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. This bias
voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias
voltage source must be stabilized by an external filter capacitor of 1.0
μ
F.
The line drivers in the TSB43AA82A operate in a high-impedance current mode, and are designed to work with
external 112-
line-termination resistor networks in order to match the 110-
cable impedance. One network is
provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-
resistors.
The midpoint of the pair of resistors that is directly connected to the twisted-pair-A terminals is connected to its
corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the
twisted-pair-B terminals is coupled to ground through a parallel R-C network with recommended values of 5 k
and
220 pF. The values of the external line termination resistors are selected to meet the standard specifications when
connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1
terminals sets the driver output current, along with other internal operating currents. This current setting resistor has
a value of 6.34 k
±
1.0%.
When the power supply of the TSB43AA82A is OFF while the twisted-pair cables are connected, the TSB43AA82A
transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at
the other end of the cable.
Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID
packet, and are set high or low as a function of the equipment design. The PWRCLS0–PWRCLS2 bits are used to
indicate the default power-class status for the node (the need for power from the cable or the ability to supply power
to the cable). See Table 119 for power-class encoding. The CONTEND bit is used as an input to indicate that the
node is a contender for bus manager (BM).
The TSB43AA82A supports suspend/resume as defined in the IEEE P1394a specification. The suspend mechanism
allows pairs of directly connected ports to be placed into a low-power state (suspended state) while maintaining a
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PDF描述 |
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| TSB81BA3I | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82AIPGEEP | 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGEG4 | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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