參數(shù)資料
型號: TSB43AA82A1
廠商: Texas Instruments, Inc.
英文描述: 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
中文描述: 1394綜合物理層和鏈路層控制器(1394集成物理層和鏈路層控制器)
文件頁數(shù): 62/146頁
文件大?。?/td> 597K
代理商: TSB43AA82A1
336
3.4.46.3 DRx Header Register 2 at F0h
BITS
ACRONYM
DIR
DESCRIPTION
031
DRx_destination_offset_lo
R/O
(Note)
DRF transmit destination offset low. DRx_destination_offset_lo represents the destination offset
low of the request packet transmitted from the DRF.
NOTE: R/W when DTPktz = 0
3.4.46.4 DRx Header Register 3 at F4h
This register defaults to 0008 0000h.
BITS
ACRONYM
DIR
DESCRIPTION
015
DRx_data_length
R/O
(Note)
DRF transmit data length. DRx_data_length represents the data length of the request packet
transmitted from the DRF. Defaults to 8h and is unaffected by a bus reset.
1631
DRx_extended_tCode
R/O
(Note)
DRF transmit extended tCode. DRx_extended_tCode represents the extended tCode of the request
packet transmitted from the DRF.
NOTE: R/W when DTPktz = 0
3.4.47 DRx Packetizer Status Registers at E8h, ECh, F0h, and F4h (DhdSel at 90h = 11b)
DhdSel in DMA control at 90h selects the header type. These registers default to 0000 0000h and are unaffected by
a bus reset.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
E8h
STAT
RESP
A
Ack
PSTAT
PRESP
P
PAck
ECh
DRx page number
F0h
DRx page length
DRx page table hi
DRx page table lo
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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相關代理商/技術參數(shù)
參數(shù)描述
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TSB43AA82APGE 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
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