參數(shù)資料
型號: TSB43AA82A1
廠商: Texas Instruments, Inc.
英文描述: 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
中文描述: 1394綜合物理層和鏈路層控制器(1394集成物理層和鏈路層控制器)
文件頁數(shù): 109/146頁
文件大?。?/td> 597K
代理商: TSB43AA82A1
99
Figure 95 show the SCSI burst mode (3) expanded to better show signal timing. Table 96 shows timing values for
Figure 95.
BDREQ(out)
BDACK(in)
BDIO(in)
BDIF(in)
tsu(BD)
th(BD)
td(WRHREQL)
BDWR(in)
td(ACKHWRH)
tsu(BD)
th(BD)
DATA[n]
BDIF[n]
tw(BDWR/ACK)
tw(BDWR/ACK)
NOTE: td(ACKHREQL) is the duration from when both BDACK and BDWR / BDRD are asserted (rising edge) until BDREQ is negated (falling edge).
BDREQ remains active (asserted) while the FIFO has capacity.
Figure 95. SCSI Burst Mode Write (3)
Table 96. SCSI Burst Mode Write (3)
ITEM
TITLE
MIN
MAX
UNIT
td(WRHREQL)
td(ACKHWRH)
td(WRLACKL)
tsu(BD)
th(BD)
tw(BDWR/ACK)
BDREQ delay
20
55
ns
BDACK to BRWR
0
ns
BRWR to BDACK
0
ns
SCSI data input setup
7
ns
SCSI data input hold
0
ns
BDWR/BDACK
22
ns
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