參數(shù)資料
型號: TSB43AA82A1
廠商: Texas Instruments, Inc.
英文描述: 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
中文描述: 1394綜合物理層和鏈路層控制器(1394集成物理層和鏈路層控制器)
文件頁數(shù): 12/146頁
文件大?。?/td> 597K
代理商: TSB43AA82A1
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1.2
Description
The TSB43AA82A is a high performance 1394 integrated PHY and link layer controller. It is compliant with the
IEEE 1394-1995 and IEEE 1394a-2000 specifications and supports asynchronous transfers.
TSB43AA82A has a generic 16-/8-bit host bus interface. It supports parallel or multiplexed connections to the
microcontroller (MCU) at rates up to 40 MHz.
The TSB43AA82A offers large data transfers with three mutually independent FIFOs: 1) the asynchronous command
FIFO with 1512 Bytes, 2) the DMA FIFO with 4728 bytes and 3) the Config ROM/LOG FIFO with 504 bytes.
The features of the TSB43AA82A support the serial bus protocol 2 (SBP-2). It handles up to four initiators with the
SBP-2 transaction/timer manager. This SBP-2 transaction engine supports fully automated operation request block
(ORB) fetches and fully automated memory page table fetches for both read and write transactions. Automated
responses to other node requests are provided; this includes responding to another node’s read request to the Config
ROM and issuing ack_busy_X for a single retry. Various control registers enable the user to program IEEE 1394
asynchronous transaction settings. The user can program the number of retries and the split transaction time-out
value by setting the time limit register in the CFR.
The TSB43AA82A also supports the direct print protocol (DPP). The asynchronous receive FIFO (ARF) in the
TSB43AA82A is large enough to satisfy the connection register area, the DRF receiving FIFO can be used as the
segment data unit (SDU) register to fulfill the large data transfer.
This document is not intended to serve as a tutorial on IEEE 1394; users are referred to IEEE Std 1394-1995 and
IEEE 1394a-2000 (see Note 1).
1 IEEE Std 1394-1995,
IEEE Standard for a High Performance Serial Bus
IEEE Std 1394a2000,
IEEE Standard for a High Performance Serial Bus Amendment 1
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