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| 型號： | TSB43AA82A1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| 中文描述： | 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器） |
| 文件頁數(shù)： | 97/146頁 |
| 文件大小： | 597K |
| 代理商： | TSB43AA82A1 |
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8.4.1.2 Packet Transmission Through the Bulky Interface in Direct Mode
Setting DTHdIs (90h, bit 24) enables the header insert mode for data written to the DTF.
Set 1 on DTFEn (90h, bit 3) to enable DTF transmission.
Set 0 on DTHdIs (90h, bit 24) to disable header insertion.
Set 1 on DTDSel (90h, bit 29) to switch to bulky interface packet write mode.
Prepare transmit data with a packet header that complies with the DTF format defined in Section 8.2.2.
Write the packet through the bulky interface. Set BDIF2BDIF0 as shown in the following tables to indicate
the end of each packet. Packets are padded with 0s as necessary to satisfy the quadlet boundary. A packet
transmission starts when the BDIF flag indicates the last data.
8-Bit Bulky
BDIF[2:0]
COMMENT
011
8-bit bulky mode
101
NOTES:
Reset
1. Any signal setting not included in the table is reserved.
2. Signal values should not be modified during data transfer.
16-Bit Bulky
BDIF[2:0]
COMMENT
010
16-bit bulky mode
011
8-bit bulky mode
101
NOTES:
Reset
1. Any signal setting not included in the table is reserved.
2. Signal values should not be modified during data transfer.
At the completion of a packet transmission, DTAval is set, and an appropriate acknowledgement is
displayed on DTxAck.
When DTSpDis (90h, bit 7) is 1 or no split transaction has occurred, a DTFEnd interrupt is created to end
the transmission transaction. When DTSpDis (90h, bit 7) is 0 and a split transaction has occurred, a DTFEnd
interrupt is created to end the transaction after a response packet is received. In this case, a response
packet is received by the DRF.
8.4.1.3 Packet Transmission Through the Bulky Interface in Packetizer Mode
As a value on DTx header[0:3] (E8hF4h) is inserted as header, adding data completes the packet to be sent. If
DTHdIs is not set, all packet data including the header needs to be written. In this case, packet format is the same
as that for the ATF.
Following is the process for a fixed-length block data transmission through the bulky interface using write request for
block.
Set DTFEn (90h, bit 3) to 1 to enable DTF transmission.
Set DTHdIs (90h, bit 24) to 1 to enable auto header insertion.
Set DTDSel (90h, bit 29) to 1 to switch to bulky interface packet write mode.
Prepare transmit data without packet header.
Specify desired packet header on DTx Header[0:3].
Write block data through the bulky interface. Set BDIF2BDIF0 as shown in the following tables. The end
of each packet needs to be specified when the length of data does not satisfy a quadlet boundary.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82AIPGEEP | 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGEG4 | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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