參數(shù)資料
型號(hào)： TSB43AA82A1
廠商： Texas Instruments, Inc.
英文描述： 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
中文描述： 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器）
文件頁數(shù)： 65/146頁
文件大小： 597K
代理商： TSB43AA82A1
339
BITS
DESCRIPTION
DIR
ACRONYM
19
LogFull
R/O
Log full. When LogFull is 1, the LOG is full.
2031
LogThere
/
ROMAddr
R/O
//
R/W
Log available flag/address of configuration ROM. When XLOG is set to 1, LogThere/ROMAddr is in
ROMAddr mode. ROMAddr is the address accessed by the host in configuration ROM. The last two bits
are 00 to ensure quadlet access. When XLOG is set to 0, LogThere/ROMAddr is LogThere. LOG has
space available for LogThere quadlets.
3.4.48.2 Log/ROM Data Register—XLOG (bit 16 at F8h) = 1
BITS
ACRONYM
DIR
DESCRIPTION
0
DTFSt
R/W
DTF status block access mode. When DTFSt is set to 1, the Adder field in this register, the FCh address,
and data access are for the DTF status block.
1
DRFSt
R/W
DRF status block access mode. When DRFSt is set to 1, the Adder field in this register, the FCh address,
and data access are for the DRF status block.
215
Reserved
N/A
Reserved
16
XLOG
R/W
Select LOG data or ConfigROM data. When XLOG is set to 1, the data read from the log/ROM data register
(FCh) is ConfigROM data. When XLOG is set to 0, the data read from the log/ROM data register (FCh ) is
LOG data.
17
ROMValid
R/W
Configuration ROM valid. When ROMValid is set to 1, the data in configuration ROM is valid. The receiver
returns ack_pending for all quadlet read requests addressed to this configuration ROM and the respective
quadlet read response packets are transmitted automatically. When ROMValid is set to 0, the data in the
configuration ROM is invalid. The receiver returns ack_tardy for all quadlet read requests addressed to
this configuration ROM.
1819
Reserved
R/O
Reserved
2031
Adder
R/W
Address for DTF/DRF status block and ConfigROM write/read.
3.4.49 Log ROM Data Register at FCh
This register defaults to 0 and is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
031
LogRead/ROMAccess
R/W
LOG data read access register/configuration ROM data read access register. See the following table.
This register defaults to 0h and is unaffected by a bus reset.
XLOG
DTFSt
DRFst
LogRead/ROMAccess field
0
X
X
LogRead access
1
0
0
Config ROM access
1
1
0
DTF status block access
1
0
1
DRF status block access
1
1
1
NA
NOTE: Do not access (read/write) data exceeding input packet quantities.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB43AA82AI 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products
TSB43AA82AIPGE 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82AIPGEEP 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82APGE 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82APGEG4 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
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