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參數(shù)資料
| 型號(hào)： | TSB43AA82A1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| 中文描述： | 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器） |
| 文件頁數(shù)： | 134/146頁 |
| 文件大小： | 597K |
| 代理商： | TSB43AA82A1 |
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124
The gap count is set to the maximum value of 63 after two consecutive bus resets without an intervening write to the
gap count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism allows a PHY-config packet
to be transmitted and then a bus reset initiated to verify that all nodes on the bus have updated their RHB bits and
gap-count values, without having the gap-count set back to 63 by the bus reset. The subsequent connection of a new
node to the bus, which initiates a bus reset, then causes the gap-count of each node to be set to 63. Note, however,
that if a subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit, all other nodes on the bus
will have their gap-count values set to 63, while this node’s gap-count remains set to the value just loaded by the write
to PHY register 1.
Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use of the
IBR bit, RHB bit, and gap-count in PHY register 1:
Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that all
nodes have correctly updated their RHB bits and gap-count values, and to ensure that a subsequent new
connection to the bus will cause the gap count to be set to 63 on all nodes in the bus. If this bus reset is
initiated by setting the IBR bit to 1, the RHB bit and Gap_Count field must also be loaded with the correct
values consistent with the just-transmitted PHY-config packet. In the TSB43AA82A, the RHB bit and gap
count will have been updated to their correct values upon the transmission of the PHY-config packet, and
so these values may first be read from register 1 and then rewritten.
Other than to initiate the bus reset which must follow the transmission of a PHY-config packet, whenever
the IBR bit is set to 1 in order to initiate a bus reset, the gap-count value must also be set to 63 so as to be
consistent with other nodes on the bus, and the RHB bit must be maintained with its current value.
The PHY register 1 must not be written to except to set the IBR bit. The RHB and gap count must not be
written without also setting the IBR bit to 1.
12.4 Low-Power Mode
When LPS is low, the TSB43AA82A automatically enters a low-power mode if the ports are inactive (disconnected,
disabled, or suspended). In this low-power mode, the TSB43AA82A disables its internal clock generators and also
disables various voltage and current reference circuits depending on the state of the port (some reference circuitry
must remain active in order to detect new cable connections, disconnections, or incoming TPBias, for example). The
lowest power consumption (the
ultralow-power sleep
mode) is attained when the port is either disconnected, or
disabled with the port’s interrupt enable bit (WDIE) cleared. The TSB43AA82A exits the low-power mode when the
LPS input is asserted high, or when a port event occurs which requires that the TSB43AA82A become active in order
to respond to the event or to notify the LLC of the event (e.g., incoming bias is detected on a suspended port, a
disconnection is detected on a suspended port, a new connection is detected on a non-disabled port, etc.). The port
will activate, but the LLC is not active. LPS must be high to exit ULP mode and to activate the LLC. See section 14
for electrical measurements.
12.5 Power Down and Initialization
Enabling power down and disabling the voltage regulator (PD = VDD and ENZ = VDD) allows the user to achieve
the lowest power modes of the TSB43AA82A. See Section 4 for these measurements. To transition from the
power-down mode to an operational mode, it is recommended that after power down is disabled and the internal
regulator is enabled (PD = VSS and ENZ = VSS) the link is reset (XRESETL) before the PHY is reset (XRESETP).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82AIPGEEP | 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGEG4 | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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