參數(shù)資料
型號(hào)： TSB43AA82A1
廠商： Texas Instruments, Inc.
英文描述： 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
中文描述： 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器）
文件頁數(shù)： 36/146頁
文件大?。?/td> 597K
代理商： TSB43AA82A1
310
BITS
27
DESCRIPTION
DIR
S/C
ACRONYM
CORend
Command block ORB fetch completed. When the fetched command block ORB is stored in the CRF,
CORend is set to 1. The host can read the completion status from transaction timer control (60h) and
transaction timer status (64h6Ch) registers until the next transaction begins.
DMA transaction from DTF completed. When the transactions of all blocks from DTF are complete,
DTFEnd is set to 1. The host can read the completion status from transaction timer control (60h) and
transaction timer status (64h6Ch) registers until the next transaction begins.
DMA transaction from DRF completed. When the transactions of all blocks from DRF are complete,
DRFEnd is set to 1. The host can read the completion status from transaction timer control (60h) and
transaction timer status (64h6Ch) registers until the next process begins.
Transmitter expired. When the transmitter fails to transfer the packets, TxExpr is set to 1.
Agent written. When the registers of any agent, command or management, are written to, AgntWr is set to
1. The host can read State, DrBll and UnSEn from the agent status register (5Ch) and
ORB_destination_offset_hi and ORB_destination_offset_lo from the ORB pointer registers (54h, 58h).
28
DTFEnd
S/C
29
DRFEnd
S/C
30
31
TxExpr
AgntWr
S/C
S/C
3.4.5
Cycle Timer Register at 14h
This register defaults to 0000 0000h and is unaffected by a bus reset.
BITS
06
719
2031
ACRONYM
Seconds_Count
Cycle_Count
Cycle_Offset
DIR
R/W
R/W
R/W
DESCRIPTION
Cycle seconds count. When Cycle_Count rolls over, Seconds_Count is incremented.
Cycle count counting 125
μ
s. When Cycle_Offset rolls over, Cycle_Count is incremented.
Cycle offset counting 40 ns. Cycle_Offset is incremented every 40 ns.
3.4.6
Diagnostics Register at 18h
This register defaults to 4000 0000h and, except for the bits specified, is unaffected by a bus reset.
BITS
0
1
ACRONYM
Reserved
AckTardy
DIR
N/A
R/W
DESCRIPTION
Reserved
Ack_tardy response enable. When this bit is set to 1, an Ack_tardy response is sent. When set to 0, an
Ack_busy response is sent. This bit defaults to 1.
2
3
4
BudgEn
Reserved
RegRW
R/W
N/A
R/W
Budget counter enable. When this bit is set to 1, the internal budget counter is enabled.
Reserved
Register read/write access. Note: RegRW is used in the test mode and must not be set during normal
operations.
5
AgntStWr
R/W
Agent write access. When AgntStWr is set to 1, agent state is read/write. When this bit is set to 0, the agent
state is not accessible.
6
7
Reserved
AgRdy0
N/A
R/O
Reserved
Agent0 ready. This bit indicates whether Agent0 has been assigned a node ID and is valid. When AgRdy0
is set to 1, command block agent 0 is ready to be written or read. When AgRdy0 is set to 0, command block
agent 0 is not ready. This bit defaults to 0 and is set to 0 on a bus reset.
Agent1 ready. This bit indicates whether Agent1 has been assigned a node ID and is valid. When AgRdy1
is set to 1, command block agent1 is ready to be written or read. When AgRdy1 is set to 0, command block
agent1 is not ready. This bit defaults to 0 and is set to 0 on a bus reset.
Agent2 ready. This bit indicates whether Agent2 has been assigned a node ID and is valid. When AgRdy2
is set to 1, command block agent2 is ready to be written or read. When AgRdy2 is set to 0, command block
agent2 is not ready. This bit defaults to 0 and is set to 0 on a bus reset.
Agent3 ready. This bit indicates whether Agent3 has been assigned a node ID and is valid. When AgRdy3
is set to 1, command block agent3 is ready to be written or read. When AgRdy3 is set to 0, command block
agent3 is not ready. This bit defaults to 0 and is set to 0 on a bus reset.
Reserved
Management agent ack_conflict. When this bit is set to 1, ack_conflict response is transmitted when the
management agent is busy. This bit is the same as MAAckConf at 08h bit 19.
8
AgRdy1
R/O
9
AgRdy2
R/O
10
AgRdy3
R/O
1113
14
Reserved
MAAckconf
N/A
R/W
1517
1823
2431
Reserved
Budget_Counter
Reserved
N/A
R/O
N/A
Reserved
Budget counter value. This field specifies the current value of the internal budget counter.
Reserved
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB43AA82AI 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products
TSB43AA82AIPGE 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82AIPGEEP 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82APGE 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82APGEG4 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
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