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| 型號(hào)： | TSB43AA82A1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| 中文描述： | 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器） |
| 文件頁(yè)數(shù)： | 33/146頁(yè) |
| 文件大?。?/td> | 597K |
| 代理商： | TSB43AA82A1 |
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37
3.4.2
Miscellaneous Register at 04h
This register defaults to 1400 0000h and, except for the bits specified, is cleared on a bus reset.
BITS
0-2
3
ACRONYM
Reserved
C
DIR
N/A
R/O
DESCRIPTION
Reserved
Bus manager capable. This bit is active when the PHY is ON even when the link is in reset. The bit defaults
to 1 and is is unaffected by a bus reset. This bit is determined by the CONTEND terminal defined in Section
2.
Link-on output from PHY. This bit is active when the PHY generates the LINKON signal, even when the link
is in reset. This bit is set when the PHY detects a LINKON packet. This bit defaults to 0 and is unaffected by
a bus reset.
Link power status. Setting this bit to 1 sets the internal PHY LPS signal to one. This bit defaults to 1 and is
unaffected by a bus reset. Refer to Section 11 for more detail.
4
LKON
S/C
5
LPS
R/O
6
Reserved
Ping_Timer
N/A
R/O
Reserved
Ping timer value. The timer measures the time in units from when a ping packet is transmitted to when the
ping response is received. One unit is 40ns.
7-15
16
Root
R/O
Root state of the local PHY. This bit indicates whether the node is the root node. The root bit is set to 1 when
the node is root. This bit defaults to 0 and is automatically set by the hardware.
17-22
23
Reserved
AckErr
N/A
R/O
Reserved
Acknowledge error. The AckErr bit is set when the ack received for the packet transmitted from the ATF
has a parity or length error.
24-27
ATAck
R/O
Address transmitter acknowledges received. These bits contain the last ack received in response to a
packet sent by the ATF. This value is updated each time an ack is received.
28-30
31
Reserved
AckVld
N/A
R/O
Reserved
Acknowledge valid. This bit is 1 when the ATAck has not been read and is cleared to 0 when the ATAck is
read.
3.4.3
Control Register at 08h
This register defaults to 4400 CA00h and is unaffected by a bus reset.
BITS
0
ACRONYM
IDVal
DIR
R/O
DESCRIPTION
ID valid. The IDVal bit is set to 1 when the information of the bus reset register at 24h is valid. This bit
defaults to 0 and is automatically set by the hardware on a bus reset.
1
RxSId
R/W
Receive self-identification (self-ID) packets. When set to 1, the self-ID packets generated by the PHY
during bus initialization are received and written to DRF or LOG as individual packets. Otherwise the
self-ID packets are not received. This bit defaults to 1 and is unaffected by a bus reset.
Received self-ID packet location selection. If RxSId is set to 1, the received self-ID packets are verified and
written to the DRF when RSIsel is set to 1 and are verified and written to the LOG when RSIsel is set to 0.
2
RSIsel
R/W
3
4
Reserved
Bsy0
N/A
R/W
Reserved
Busy control. When this bit is set to 1, the ack_busy_X is sent to all incoming packets. When Bsy0 is set to
0, ack_busy_X is sent according to the normal busy/retry protocol.
5
TrEn
R/W
Transactions enable. When TrEn is set to 1, the transmitter and receiver are enabled to transmit and
receive packets. When TrEn is set to 0, the link core is not awake, the TSB43AA82A cannot send ack or
receive self-ID packets, and the transmitter and receiver are disabled. This bit defaults to 1 and is
unaffected by a bus reset.
6
Reserved
N/A
Reserved
Accelerated arbitration on. When ACArbOn is set to 1, accelerated arbitration is enabled.
Reserved
BDIF control enable. When BDIFcntEN is set to 1, ATACK, BDOAVAIL, BDIBUSY and BDOF[2:0] are
placed in the high-impedance state.
7
8
9
ACArbOn
Reserved
BDIFcntEN
R/W
N/A
N/A
10
RstTr
S/C
Reset transaction. When RstTr is set to 1, the entire transaction in the ATF, the ARF, the CTQ, the CRF, the
MTQ, and the MRF resets synchronously. This does not affect the DTF and the DRF.
1113
14
Reserved
ErrResp
N/A
R/W
Reserved
Error packet response. When ErrResp is set to 1, packets with errors are returned an ack_pending in the
response packet. When ErrResp is set to 0, packets with errors are returned an ack error code in the
response packet.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82AI | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82AIPGEEP | 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGEG4 | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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