參數(shù)資料
型號(hào): TSB43AA82A1
廠商: Texas Instruments, Inc.
英文描述: 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
中文描述: 1394綜合物理層和鏈路層控制器(1394集成物理層和鏈路層控制器)
文件頁數(shù): 48/146頁
文件大?。?/td> 597K
代理商: TSB43AA82A1
322
3.4.25.3 Transaction Timer Status Register 3 at 6Ch
BITS
ACRONYM
DIR
DESCRIPTION
03
tCode
R/O
TimerNo’s transmitting tCode. The tCode of the packet that the timer defined by TimrNo at 60h is
transmitting or has transmitted in the last transaction.
45
Spd
R/O
TimerNo’s transmitting speed. The speed of the packet that timer defined by TimrNo at 60h is transmitting
or has transmitted in the last transaction.
611
tLabel
R/O
TimerNo’s transmitting tLabel. The tLabel of the packet that the timer defined by TimrNo at 60h is
transmitting or has transmitted in the last transaction.
1215
Retry_Counter
R/O
TimerNo’s transmitting retry counter. The limit set by the Retry_Counter of the packet that the timer defined
by TimrNo at 60h is transmitting or has transmitted in the last transaction.
1631
SplitTrTimer
R/O
TimerNo’s transmitting split transaction timer. The SplitTrTimer period that the timer defined by TimrNo at
60h is waiting or has waited for the response packet in the last transaction. This timer increments on the
cycle-start packets.
3.4.26 Write-First, Write-Continue, and Write-Update Registers at 70h, 74h, 78h
These registers default to 0000 0000h and are set to 0000 0000h on a bus reset.
3.4.26.1 Write-First Register at 70h
BITS
ACRONYM
DIR
DESCRIPTION
031
Write_First
W/O
Write the first quadlet of the packet to ATF, MTQ or CTQ. This write-only register provides the host with the
capability to write the first quadlet of a transmit packet to the transmitting FIFO.
The values of tLabel and tCode determine to which FIFO (ATF,MTQ or CTQ) the written packet is
delivered.
3.4.26.2 Write-Continue Register at 74h
BITS
ACRONYM
DIR
DESCRIPTION
031
Write_Continue
W/O
Write any quadlet other than the first or the last quadlet to ATF, MTQ or CTQ. This write-only register
provides the host with the capability to write any quadlet other than the first or last of a transmit packet to the
transmitting FIFO.The transmitting FIFO was determined when the host wrote to the Write_First (70h)
register.
3.4.26.3 Write-Update Register at 78h
BITS
ACRONYM
DIR
DESCRIPTION
031
Write_Update
W/O
Write the last quadlet of the packet. This-write only register provides the host with the capability to write the
last quadlet of a transmit packet to transmitting FIFO. The transmitting FIFO was determined when the
host wrote to the Write_First (70h) register.
3.4.27 Reserved at 7Ch
3.4.28 ARF, MRF, and CRF Data Read Registers at 80h, 84h, 88h
These registers default to 0000 0000h and are set to 0000 0000h on a bus reset.
3.4.28.1 ARF Data Read Register at 80h
BITS
ACRONYM
DIR
DESCRIPTION
031
ARFRead
R/O
ARF data read access register. This read-only register provides the host with the capability to read a
quadlet of the received packet from the ARF. Each read outputs the next quadlet from the ARF. If the ARF is
empty, the last valid value is read.
3.4.28.2 MRF Data Read Register at 84h
BITS
ACRONYM
DIR
DESCRIPTION
031
MRFRead
R/O
MRF data read access register. This read-only register provides the host with the capability to read a
quadlet of the received packet from the MRF. Each read outputs the next quadlet from the MRF. If the MRF
is empty, the last valid value is read.
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