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參數資料
| 型號： | TSB43AA82A1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| 中文描述： | 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器） |
| 文件頁數： | 133/146頁 |
| 文件大小： | 597K |
| 代理商： | TSB43AA82A1 |
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123
4.
Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent
upon the load capacitance specified for the crystal. Total load capacitance (C
L
) is a function of not only the
discrete load capacitors, but also board layout and circuit. It is recommended that load capacitors with a
maximum of
±
5% tolerance be used.
As an example, for the TSB43AA82A evaluation module (EVM) which uses a crystal specified for 20 pF loading, load
capacitors (C9 and C10 in Figure 124) of 27 pF each were appropriate for the layout of that particular board. The
load specified for the crystal includes the load capacitors (C9, C10), the loading of the PHY pins (C
PHY
), and the
loading of the board itself (C
BD
). The value of C
PHY
is typically about 1 pF, and C
BD
is typically 0.8 pF per centimeter
of board etch; a
typical
board can have 3 pF to 6 pF or more. The load capacitors C9 and C10 combine as capacitors
in series so that the total load capacitance is:
C
L
(C9
C9
C10)
C10
C
PHY
C
BD
XO
C9
C10
24.576 MHz
X1
CPHY+ CBD
XI
Is
Figure 124. Load Capacitance for the TSB43AA82A PHY Portion
NOTE:
The layout of the crystal portion of the PHY circuit is important for obtaining the correct
frequency, minimizing noise introduced into the PHY’s phase-lock loop, and minimizing any
emissions from the circuit. The crystal and two load capacitors should be considered as a unit
during layout. The crystal and load capacitors should be placed as close as possible to one
another while minimizing the loop area created by the combination of the three components.
Varying the size of the capacitors may help in this. Minimizing the loop area minimizes the effect
of the resonant current (I
s
) that flows in this resonant circuit. This layout unit (crystal and load
capacitors) should then be placed as close as possible to the PHY XI and XO pins to minimize
trace lengths.
C9
C10
X1
Figure 125. Recommended Crystal and Capacitor Layout
12.3 Bus Reset
In the TSB43AA82A, the initiate bus reset (IBR) bit can be set to 1 in order to initiate a bus reset and initialization
sequence. The IBR bit is located in PHY register 1, along with the root-holdoff bit (RHB) and Gap_Count field, as
required by the P1394a supplement (this configuration also maintains compatibility with older TI PHY designs which
were based upon the suggested register set defined in Annex J of IEEE Std 1394-1995
1
). Therefore, whenever the
IBR bit is written, the RHB bit and Gap_Count field are also necessarily written.
The RHB bit and gap-count may also be updated by PHY-config packets. The TSB43AA82A is P1394a compliant,
and therefore both the reception and transmission of PHY-config packets cause the RHB and gap-count to be loaded,
unlike older IEEE Std 1394-1995 compliant PHYs which decode only received PHY-config packets.
1 IEEE Std 1394-1995,
IEEE Standard for a High Performance Serial Bus
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB43AA82AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82AIPGEEP | 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGEG4 | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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