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參數(shù)資料
| 型號： | TSB43AA82A1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| 中文描述： | 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器） |
| 文件頁數(shù)： | 37/146頁 |
| 文件大?。?/td> | 597K |
| 代理商： | TSB43AA82A1 |
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311
3.4.7
Reserved at 1Ch
3.4.8
PHY Access Register at 20h
This register defaults to 0000 0000h and is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
0
RdPy
S/C
Read PHY bit. When RdPy is set to 1, the link sends a read register request with the address equal to
PhyRgAd to the PHY. This bit is cleared when the request is sent.
1
WrPy
S/C
Write PHY bit. When WrPy is set to 1, the link sends a write register request with the address equal to
PhyRgAd to the PHY. This bit is cleared when the request is sent.
23
Reserved
N/A
Reserved
47
PhyRgAd
R/W
PHY-register address. The address of the PHY register to be accessed when either WrPy or RdPy is 1.
815
PhyRgData
R/W
PHY-register data. The data to be written to the Phy register when WrPy is 1.
1619
Reserved
N/A
Reserved
2023
PhyRxAd
R/O
PHY-register-received address. The address of the PHY register from where PhyRxData came.
2431
PhyRxData
R/O
PHY-register-received data. The data of PHY register addressed by PhyRxAd.
3.4.9
Bus Reset Register at 24h
This register defaults to FFFF 003Fh and, except for the bits specified, is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
09
BusNumber
R/W
Bus number. The link uses BusNumber as BusID. When a bus reset completes, BusNumber is
automatically updated. The host can overwrite BusNumber. This field defaults to 3FFh and is unaffected
by a bus reset.
1015
NodeNum
R/O
Node number. The link uses NodeNum as NodeID. When a bus reset completes, NodeNum is set to an
appropriate value. This field defaults to 3Fh and is automatically set by the hardware after a bus reset.
1619
BRFErr_Code
R/O
Error code in bus reset. When a bus reset occurs, BRFErr_Code is set to the appropriate value. If
BRFErr_Code is not zero, the host initiates a bus reset again. The code table is below.
0000 No error
0001 Last self-ID port status is not all children, not the root node
0010 PHY ID is sequence error (not in the correct order)
0011 Inverted quadlet is not the reverse of preceding quadlet
0100 PHY ID sequence error (two gaps in PHY IDs)
0101 PHY ID sequence error (arbitration reset gap in PHY IDs)
0110 PHY ID within self-ID packet does not match
0111 Quadlet/inverted-quadlet sequence error
1000 First 2 bits of the self-ID packet do not match either 01 or 10
1001-1110 reserved
1111 At least one self-ID packet has different GAP count.
This field defaults to 0 and is automatically set by the hardware after a bus reset.
2025
NodeSum
R/O
Number of nodes in this 1394 topology. When a bus reset occurs, NodeSum is set to the appropriate value.
These bits default to 0 and are automatically set by the hardware after a bus reset.
2631
CFRContID
R/O
Node ID of isochronous resource manager. When a bus reset occurs, CFRContID is set to the appropriate
value. This field defaults to 3Fh and is automatically set by the hardware after a bus reset.
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PDF描述 |
|---|---|
| TSB81BA3I | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
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| TSL235(中文) | Programmable Light-To-Frequency Converter(光頻轉(zhuǎn)換器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82AIPGEEP | 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGEG4 | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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