參數(shù)資料
型號(hào): TSB43AA82A1
廠商: Texas Instruments, Inc.
英文描述: 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
中文描述: 1394綜合物理層和鏈路層控制器(1394集成物理層和鏈路層控制器)
文件頁(yè)數(shù): 37/146頁(yè)
文件大?。?/td> 597K
代理商: TSB43AA82A1
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)當(dāng)前第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)
311
3.4.7
Reserved at 1Ch
3.4.8
PHY Access Register at 20h
This register defaults to 0000 0000h and is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
0
RdPy
S/C
Read PHY bit. When RdPy is set to 1, the link sends a read register request with the address equal to
PhyRgAd to the PHY. This bit is cleared when the request is sent.
1
WrPy
S/C
Write PHY bit. When WrPy is set to 1, the link sends a write register request with the address equal to
PhyRgAd to the PHY. This bit is cleared when the request is sent.
23
Reserved
N/A
Reserved
47
PhyRgAd
R/W
PHY-register address. The address of the PHY register to be accessed when either WrPy or RdPy is 1.
815
PhyRgData
R/W
PHY-register data. The data to be written to the Phy register when WrPy is 1.
1619
Reserved
N/A
Reserved
2023
PhyRxAd
R/O
PHY-register-received address. The address of the PHY register from where PhyRxData came.
2431
PhyRxData
R/O
PHY-register-received data. The data of PHY register addressed by PhyRxAd.
3.4.9
Bus Reset Register at 24h
This register defaults to FFFF 003Fh and, except for the bits specified, is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
09
BusNumber
R/W
Bus number. The link uses BusNumber as BusID. When a bus reset completes, BusNumber is
automatically updated. The host can overwrite BusNumber. This field defaults to 3FFh and is unaffected
by a bus reset.
1015
NodeNum
R/O
Node number. The link uses NodeNum as NodeID. When a bus reset completes, NodeNum is set to an
appropriate value. This field defaults to 3Fh and is automatically set by the hardware after a bus reset.
1619
BRFErr_Code
R/O
Error code in bus reset. When a bus reset occurs, BRFErr_Code is set to the appropriate value. If
BRFErr_Code is not zero, the host initiates a bus reset again. The code table is below.
0000 No error
0001 Last self-ID port status is not all children, not the root node
0010 PHY ID is sequence error (not in the correct order)
0011 Inverted quadlet is not the reverse of preceding quadlet
0100 PHY ID sequence error (two gaps in PHY IDs)
0101 PHY ID sequence error (arbitration reset gap in PHY IDs)
0110 PHY ID within self-ID packet does not match
0111 Quadlet/inverted-quadlet sequence error
1000 First 2 bits of the self-ID packet do not match either 01 or 10
1001-1110 reserved
1111 At least one self-ID packet has different GAP count.
This field defaults to 0 and is automatically set by the hardware after a bus reset.
2025
NodeSum
R/O
Number of nodes in this 1394 topology. When a bus reset occurs, NodeSum is set to the appropriate value.
These bits default to 0 and are automatically set by the hardware after a bus reset.
2631
CFRContID
R/O
Node ID of isochronous resource manager. When a bus reset occurs, CFRContID is set to the appropriate
value. This field defaults to 3Fh and is automatically set by the hardware after a bus reset.
相關(guān)PDF資料
PDF描述
TSB81BA3I IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSE-0155-32S-P1-3 SINGLE MODE SINGLE FIBER TRANSCEIVER
TSL230 PROGRAMMABLE LIGHT-TO-FREQUENCY CONVERTERS
TSL235(中文) Programmable Light-To-Frequency Converter(光頻轉(zhuǎn)換器)
TSL245(中文) IR Light-To-Frequency Converter(紅外光頻轉(zhuǎn)換器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB43AA82AI 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products
TSB43AA82AIPGE 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82AIPGEEP 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82APGE 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82APGEG4 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray