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參數(shù)資料
| 型號(hào)： | POMAP5912ZDY |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CONN DIN PLUG VERT 96POS 3ROWS |
| 中文描述： | 應(yīng)用處理器 |
| 文件頁(yè)數(shù)： | 94/254頁(yè) |
| 文件大?。?/td> | 2467K |
| 代理商： | POMAP5912ZDY |
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Introduction
94
December 2003 Revised March 2005
SPRS231D
Table 25. Signal Descriptions (Continued)
SIGNAL
TYPE
DESCRIPTION
ZZG
BALL#
ZDY
BALL#
POWER SUPPLIES
CV
DD
C11 K5
M7 T16
A15 M2
Y9 Y20
Core supply voltage. Supplies power to OMAP5912 core logic and
low-voltage sections of I/O.
Power
CV
DD1
CV
DD2
T3
AA3
Core supply voltage 1. Supplies power to OMAP5912 core logic.
Power
H7 G9 G8
A3 A9 E2
Core supply voltage 2. Supplies power to the MPU subsystem logic and
memory.
Power
CV
DD3
G10 H11
K11 J10
B13 B20
J21 R20
Core supply voltage 3. Supplies power to the DSP subsystem logic and
memory. If the DSP system is not used, can be grounded after the isolation
control in ULPD is set.
Power
CV
DDRTC
L9
W12
Core supply voltage for the RTC. Supplies power to the RTC core logic. Can
be connected to CV
DD
if the RTC is not used as a standalone.
Analog supply voltage. Supplies power to the analog phase-locked loop
(APLL) used to provide 48-MHz clock to peripherals such as USB, UART, or
MMC/SD/SDIO peripherals. Note: The voltage to this supply pin must be
kept as clean as possible to maximize performance by minimizing clock jitter.
Power
CV
DDA
P17
Y21
Power
CV
DDDLL
A9
A11
Core supply voltage for the digitally controlled delay element (calibration
module) used to control read and write timings to external dual data rate
(DDR) SDRAM. It is recommended that an RC (R = 10
, C = 100 nF)
low-pass filter be implemented externally to filter switching noises.
Power
DV
DD1
C14 G12
A19 E21
I/O supply voltage 1. Supplies power to the majority of peripheral I/O buffers.
DV
DD1
can be connected in common with the other DV
DD
supplies if the
same operating voltage is desired.
Power
DV
DD2
U2
AA2
I/O supply voltage 2. Supplies power to the internal USB transceiver buffers
of USB port 0. DV
DD2
can optionally be used for USB connect and
disconnect detection by connecting DV
DD2
to the power from the USB bus in
the system. DV
DD2
can be connected in common with the other DV
DD
supplies if the same operating voltage is desired.
Power
DV
DD3
T6
Y7
I/O supply voltage 3. Supplies power to the MCSI2 and McBSP2 peripheral
I/O buffers as well as to GPIO[9:8] I/O buffers. The DV
DD3
supply can
operate within a high-voltage or low-voltage range. DV
DD3
can be connected
in common with the other DV
DD
supplies if the same operating voltage is
desired.
Power
DV
DD4
D6 D7
D8 D11
A5 A7
B10 B14
I/O supply voltage 4. Supplies power to the DDR/SDRAM interface I/O
buffers. The DV
DD4
supply can operate within a high-voltage or low-voltage
range. DV
DD4
can be connected in common with the other DV
DD
supplies if
the same operating voltage is desired.
Power
DV
DD5
B1 G1
L3
C2 H2
R1
I/O supply voltage 5. Supplies power to the flash interface I/O buffers. The
DV
DD5
supply can operate within a high-voltage or low-voltage range.
DV
DD5
can be connected in common with the other DV
DD
supplies if the
same operating voltage is desired.
Power
DV
DD6
T10
AA11
I/O supply voltage 6. Supplies power to the MMC/SD1 interface I/O buffers.
DV
DD6
can be connected in common with the other DV
DD
supplies if the
same operating voltage is desired.
Power
I = Input, O = Output, Z = High-Impedance
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| POMAP5912ZDYA | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:POMAP5912, BGA 19X19 (-40/85 AMBIENT ) - Trays |
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| POMONA5514-RS | 制造商:Pomona Electronics 功能描述:SOIC SMT clip kit |
| PON15 | 功能描述:保險(xiǎn)絲 NRN 15 A CART RoHS:否 制造商:Littelfuse 產(chǎn)品:Surface Mount Fuses 電流額定值:0.5 A 電壓額定值:600 V 保險(xiǎn)絲類型:Fast Acting 保險(xiǎn)絲大小/組:Nano 尺寸:12.1 mm L x 4.5 mm W 安裝風(fēng)格: 端接類型:SMD/SMT 系列:485 |
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