
Introduction
51
December 2003 Revised March 2005
SPRS231D
Table 23. ZDY Package Terminal Characteristics (Continued)
ZDY
BALL
NO.
SUPPLY
RESET
STATE
#
OTHER
BUFFER
STRENGTH
§
PULLUP/
PULLDN
MUX CTRL SETTING
TYPE
SIGNAL NAME
T12
LOW_STATE
O
Reg9[23:21] = 000
3 mA (Hv)
G1
0
DV
DD7
UART1.TX
O
Reg9[23:21] = 001
2 mA (Lv)
A, B, F,
UART1.IRTX
O
Reg9[23:21] = 010
P11
MCSI1.DOUT
O
Reg9[26:24] = 000
3 mA (Hv)
G1, H3
0
DV
DD7
USB1.TXD
O
Reg9[26:24] = 001
2 mA (Lv)
A, B, F,
TDO
O
Reg9[26:24] = 011
MCBSP3.DX
O
Reg9[26:24] = 100
GPIO18
I/O
Reg9[26:24] = 111
U12
CLK32K_OUT
O
RegA[14:12] = 000
PD20
3 mA (Hv)
A
U
DV
DDRTC
MPUIO0
I/O
RegA[14:12] = 100
PU20,
2 mA (Lv)
USB1.SPEED
O
RegA[14:12] = 101
UART1.TX
O
RegA[14:12] = 110
GPIO36
I/O
RegA[14:12] = 111
U11
OSC32K_IN
NA
E
NA
NA
U10
OSC32K_OUT
NA
E
NA
NA
N9
RTC_WAKE_INT
O
Reg9[2:0] = 000
3 mA (Hv)
A, B
0
DV
DDRTC
USB1.SE0
O
Reg9[2:0] = 100
2 mA (Lv)
RST_HOST_OUT
O
Reg9[2:0] = 101
GPIO55
I/O
Reg9[2:0] = 111
P10
RTC_ON_NOFF
I
Reg8[20:18] = 000
2 mA (Lv)
3 mA (Hv)
A, B, G1
Z
DV
DDRTC
T11
CLK32K_IN
I
RegA[17:15] = 000
A
Input
DV
DDRTC
N8
PWRON_RESET
I
NA
A
Input
DV
DDRTC
P9
MMC.DAT3
I/O
Reg10[17:15] = 000
PD20
3 mA (Hv)
A, F, G1
Z
DV
DD6
MPUIO9
I/O
Reg10[17:15] = 001
PU20,
2 mA (Lv)
MPUIO6
I/O
Reg10[17:15] = 010
M8
MMC.CLK
O
RegA[23:21] = 000
PU20
3 mA (Hv)
A, F, G1
0
DV
DD6
GPIO57
I/O
RegA[23:21] = 110
PD100,
2 mA (Lv)
R8
MMC.DAT0
I/O
RegB[2:0] = 000
PD20
3 mA (Hv)
A, F, G1
Z
DV
DD6
Z_STATE
Z
RegB[2:0] = 001
PU20,
2 mA (Lv)
GPIO58
I/O
RegB[2:0] = 111
I = Input, O = Output, Z = High-Impedance
PD20 = 20-
μ
A internal pulldown, PD100=100-
μ
A internal pulldown, PU20 = 20-
μ
A internal pullup, PU100 = 100-
μ
A internal pullup. Pullup or
pulldown can be enabled or disabled by software.
§
Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V)
A = Standard LVCMOS input/output
G1 = Terminal may be gated by BFAIL
B = SUBLVDS input/ouput
G2 = Terminal may be gated by GPIO9 and MPUIO3
C = USB transceiver input/ouput
G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset
D = I
2
C input/output buffers
H1 = Terminal may be 3-stated by BFAIL input
E = Analog oscillator terminals
H3 = MCSI1.DOUT pin can be forced into a high-impedance
F = Boundary-scannable terminal
state by the OMAP5912 HIGH_IMP3 control bit
K = Output buffer includes a serial resistor of 20
to match with PCB line impedance and ensure proper signal integrity
#
Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
NOTES:
3. NA denotes no multiplexing on the ball
4. ‘Regx’ denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x