
Functional Overview
103
December 2003 Revised March 2005
SPRS231D
Table 33. MPU Level 2 Interrupt Handler Registers (Continued)
RESET
VALUE
ACCESS
TYPE
ACCESS
WIDTH
DESCRIPTION
REGISTER NAME
BYTE
ADDRESS
FFFE:0048
MPU_L2_ILR11
Interrupt Priority Level For IRQ 11 Register
32
R/W
0000 0000h
FFFE:004C
MPU_L2_ILR12
Interrupt Priority Level For IRQ 12 Register
32
R/W
0000 0000h
FFFE:0050
MPU_L2_ILR13
Interrupt Priority Level For IRQ 13 Register
32
R/W
0000 0000h
FFFE:0054
MPU_L2_ILR14
Interrupt Priority Level For IRQ 14 Register
32
R/W
0000 0000h
FFFE:0058
MPU_L2_ILR15
Interrupt Priority Level For IRQ 15 Register
32
R/W
0000 0000h
FFFE:005C
MPU_L2_ILR16
Interrupt Priority Level For IRQ 16 Register
32
R/W
0000 0000h
FFFE:0060
MPU_L2_ILR17
Interrupt Priority Level For IRQ 17 Register
32
R/W
0000 0000h
FFFE:0064
MPU_L2_ILR18
Interrupt Priority Level For IRQ 18 Register
32
R/W
0000 0000h
FFFE:0068
MPU_L2_ILR19
Interrupt Priority Level For IRQ 19 Register
32
R/W
0000 0000h
FFFE:006C
MPU_L2_ILR20
Interrupt Priority Level For IRQ 20 Register
32
R/W
0000 0000h
FFFE:0070
MPU_L2_ILR21
Interrupt Priority Level For IRQ 21 Register
32
R/W
0000 0000h
FFFE:0074
MPU_L2_ILR22
Interrupt Priority Level For IRQ 22 Register
32
R/W
0000 0000h
FFFE:0078
MPU_L2_ILR23
Interrupt Priority Level For IRQ 23 Register
32
R/W
0000 0000h
FFFE:007C
MPU_L2_ILR24
Interrupt Priority Level For IRQ 24 Register
32
R/W
0000 0000h
FFFE:0080
MPU_L2_ILR25
Interrupt Priority Level For IRQ 25 Register
32
R/W
0000 0000h
FFFE:0084
MPU_L2_ILR26
Interrupt Priority Level For IRQ 26 Register
32
R/W
0000 0000h
FFFE:0088
MPU_L2_ILR27
Interrupt Priority Level For IRQ 27 Register
32
R/W
0000 0000h
FFFE:008C
MPU_L2_ILR28
Interrupt Priority Level For IRQ 28 Register
32
R/W
0000 0000h
FFFE:0090
MPU_L2_ILR29
Interrupt Priority Level For IRQ 29 Register
32
R/W
0000 0000h
FFFE:0094
MPU_L2_ILR30
Interrupt Priority Level For IRQ 30 Register
32
R/W
0000 0000h
FFFE:0098
MPU_L2_ILR31
Interrupt Priority Level For IRQ 31 Register
32
R/W
0000 0000h
FFFE:009C
MPU_L2_ISR
Software Interrupt Set Register
32
W
0000 0000h
FFFE:00A0
MPU_L2_STATUS
Status Register
32
R
0000 0000h
FFFE:00A4
MPU_L2_OCP_CFG
OCP Configuration Register
32
R/W
0000 0000h
FFFE:00A8
MPU_L2_INTH_REV
Interrupt Controller Revision ID
32
R
0000 0000h
Table 34. LCDCONV Registers
BYTE
ADDRESS
REGISTER NAME
DESCRIPTION
ACCESS
WIDTH
ACCESS
TYPE
RESET
VALUE
FFFE:3000
FFFE:301F
LCDCONV_R_LOOK_UP
R Look-up Table Register File
8
R/W
undefined
FFFE:3020
FFFE:303F
LCDCONV_B_LOOK_UP
B Look-up Table Register File
8
R/W
undefined
FFFE:3040
FFFE:307F
LCDCONV_G_LOOK_UP
G Look-up Table Register File
8
R/W
undefined
FFFE:3080
LCDCONV_CONTROL
Control Register
8
R/W
0000h
FFFE:3084
LCDCONV_DEV_REV
Device Revision Register
8
R
undefined