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參數(shù)資料
| 型號(hào)： | POMAP5912ZDY |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CONN DIN PLUG VERT 96POS 3ROWS |
| 中文描述： | 應(yīng)用處理器 |
| 文件頁(yè)數(shù)： | 179/254頁(yè) |
| 文件大小： | 2467K |
| 代理商： | POMAP5912ZDY |
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Functional Overview
179
December 2003 Revised March 2005
SPRS231D
3.8.5 I
2
C Master/Slave Interface
The multimaster I
2
C peripheral provides an interface between a local host (LH), such as an MPU or DSP
processor, and any I
2
C bus compatible device that connects via the I
2
C serial bus. External components
attached to the I
2
C bus can serially transmit/receive up to 8 bits of data to/from the LH device or a DMA through
the I
2
C interface. This I
2
C peripheral supports any slave or master I
2
C-compatible device.
The I
2
C bus is a multimaster bus. The I
2
C controller supports the multimaster mode, which allows more than
one device capable of controlling the bus to be connected to it. Each I
2
C device is recognized by a unique
address and can operate as either transmitter or receiver, depending on the function of the device. In addition
to being a transmitter or receiver, the device connected to the I
2
C bus can also be considered a master or a
slave when performing data transfers. Note that a master device is the device which initiates a data transfer
on the bus and generates the clock signals to enable that transfer. During the latter, any device addressed
by this master is considered a slave.
The I
2
C interface with the local host is compliant with 8-/16-bit OCP protocol. The interface clock and the
functional clock are independent. The I
2
C master/slave interface supports the following features:
Compliant to Philips I
2
C-bus specification version 2.1
Support standard mode (up to 100K bits/s) and fast mode (up to 400K bits/s)
In the master only I
2
C operating mode of OMAP5912, standard mode is supported up to 83K bits/s.
7-bit and 10-bit device addressing modes
General call
Start/restart/stop
Multimaster transmitter/slave receiver mode
Multimaster receiver/slave transmitter mode
Combined master transmit/receive and receive/transmit mode
Built-in FIFO for buffered read or write
Module enable/disable capability
Programmable clock generation
Supports use of two DMA channels
The I
2
C master/slave interface does not support the following features:
High-speed (HS) mode for transfer rates up to 3.4M bits
C-bus compatibility mode
3.8.6 Multichannel Buffered Serial Port (McBSP2)
The multichannel buffered serial port (McBSP) provides a high-speed, full-duplex serial port that allows direct
interface to audio codecs, and various other system devices. The McBSP provides:
Full-duplex communication
Double-buffer data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| POMAP5912ZDYA | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:POMAP5912, BGA 19X19 (-40/85 AMBIENT ) - Trays |
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| POMONA 5514-RS | 制造商:Pomona 功能描述:CLIP KIT SOIC |
| POMONA5514-RS | 制造商:Pomona Electronics 功能描述:SOIC SMT clip kit |
| PON15 | 功能描述:保險(xiǎn)絲 NRN 15 A CART RoHS:否 制造商:Littelfuse 產(chǎn)品:Surface Mount Fuses 電流額定值:0.5 A 電壓額定值:600 V 保險(xiǎn)絲類型:Fast Acting 保險(xiǎn)絲大小/組:Nano 尺寸:12.1 mm L x 4.5 mm W 安裝風(fēng)格: 端接類型:SMD/SMT 系列:485 |
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