
Introduction
23
December 2003 Revised March 2005
SPRS231D
2.1.1 TMS320C55x DSP Core
The DSP core of the OMAP5912 device is based on the TMS320C55x DSP generation CPU processor core.
The C55xDSP architecture achieves high performance and low power through increased parallelism and total
focus on reduction in power dissipation. The CPU supports an internal bus structure composed of one program
bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA
activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle.
In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication
in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of
the ALUs is under instruction set control, providing the ability to optimize parallel activity and power
consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU.
The C55x DSPs support a variable byte width instruction set for improved code density. The instruction unit
(IU) performs 32-bit program fetches from internal or external memory and queues instructions for the program
unit (PU). The program unit decodes the instructions, directs tasks to AU and DU resources, and manages
the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional
instructions. The OMAP5912 DSP core also includes a 24K-byte instruction cache to minimize external
memory accesses, improving data throughput and conserving system power.
2.1.1.1
DSP Tools Support
The 55x DSP core is supported by the industry’s leading eXpressDSP
software environment including the
Code Composer Studio
Integrated Development Environment (IDE), DSP/BIOS software kernel foundation,
the TMS320
DSP Algorithm Standard, and the industry’s largest third-party network. Code Composer Studio
features code generation tools including a C-Compiler, Visual Linker, simulator, Real-Time Data Exchange
(RTDX
), XDS510
emulation device drivers, and Chip Support Libraries (CSL). DSP/BIOS is a scalable
real-time software foundation available for no cost to users of Texas Instruments’ DSP products, providing a
preemptive task scheduler and real-time analysis capabilities with very low memory and megahertz overhead.
The TMS320 DSP Algorithm Standard is a specification of coding conventions allowing fast integration of
algorithms from different teams, sites, or third parties into the application framework. Texas Instruments’
extensive DSP third-party network of over 400 providers brings focused competencies and complete solutions
to customers.
2.1.1.2
DSP Software Support
Texas Instruments has also developed foundation software available for the 55x DSP core. The C55x DSP
Library (DSPLIB) features over 50 C-callable software routines (FIR/IIR filters, Fast Fourier Transforms
(FFTs), and various computational functions). The DSP Image/Video Processing Library (IMGLIB) contains
over 20 software routines highly optimized for C55x DSPs and is compiled with the latest revision of the C55x
DSP code generation tools. These imaging functions support a wide range of applications that include
compression, video processing, machine vision, and medical imaging.
eXpressDSP, Code Composer Studio, TMS320, RTDX, and XDS510 are trademarks of Texas Instruments.