
Functional Overview
153
December 2003 Revised March 2005
SPRS231D
Table 362. Traffic Controller EMIFF Registers
BYTE
ADDRESS
REGISTER NAME
DESCRIPTION
ACCESS
WIDTH
ACCESS
TYPE
RESET
VALUE
FFFE:CC08
EMIFF_PRIO_REG
EMIFF Priority Register
32
R/W
0000 0000h
FFFE:CC20
EMIFF_SDRAM_CONFIG
EMIFF SDRAM Configuration Register
32
R/W
0061 8800h
FFFE:CC24
EMIFF_MRS
EMIFF SDRAM MRS Register
32
R/W
0000 0037h
FFFE:CC3C
EMIFF_SDRAM_CONFIG_2
EMIFF SDRAM Configuration Register 2
32
R/W
0000 0003h
FFFE:CC64
DLL_WRT_CTL
DLL WRT Control Register (write byte)
32
R/W
0000 0000h
FFFE:CC68
DLL_WRT_STAT
DLL WRT Status Register (read lower byte)
32
R
0000 0000h
FFFE:CC70
EMIFF_MRS_NEW
EMIFF SDRAM MRS Register (duplicate)
32
R/W
0000 0037h
FFFE:CC74
EMIFF_EMRS0
EMIFF SDRAM EMRS 0 Register
32
R/W
0000 0000h
FFFE:CC78
EMIFF_EMRS1
EMIFF SDRAM EMRS 1 Register
32
R/W
0000 0000h
FFFE:CC80
EMIFF_OP
EMIFF SDRAM Operation Register
32
R/W
0000 0004h
FFFE:CC84
EMIFF_MCMD
EMIFF SDRAM Manual Command Register
32
R/W
0000 0000h
FFFE:CC8C
EMIFF_TIMEOUT1
EMIFF Dynamic Arb. Priority Timeout 1
Register
32
R/W
0000 0000h
FFFE:CC90
EMIFF_TIMEOUT2
EMIFF Dynamic Arb. Priority Timeout 2
Register
32
R/W
0000 0000h
FFFE:CC94
EMIFF_TIMEOUT3
EMIFF Dynamic Arb. Priority Timeout 3
Register
32
R/W
0000 0000h
FFFE:CC98
EMIFF_ABORT_ADDR
EMIFF Abort Address Register
32
R
0000 0000h
FFFE:CC9C
EMIFF_ABORT_TYPE
EMIFF Abort Type Register
32
R
0000 0000h
FFFE:CCC0
DLL_URD_CTL
DLL URD Control Register (read upper byte)
32
R/W
0000 0000h
FFFE:CCC4
DLL_URD_STAT
DLL URD Status Register (read upper byte)
32
R
0000 0000h
FFFE:CCC8
EMIFF_EMRS2
EMIFF SDRAM EMRS 2 Register
32
R/W
0000 0000h
FFFE:CCCC
DLL_LRD_CTL
DLL LRD Control Register (read lower byte)
32
R/W
0000 0000h
FFFE:CCBC
DLL_LRD_STAT
DLL LRD Status Register (read lower byte)
32
R
0000 0000h
Table 363. MPU Clock/Reset/Power Mode Control Registers
BYTE
ADDRESS
REGISTER NAME
DESCRIPTION
ACCESS
WIDTH
ACCESS
TYPE
RESET
VALUE
FFFE:CE00
ARM_CKCTL
MPU Clock Control Register
32
R/W
3000h
FFFE:CE04
ARM_IDLECT1
MPU Idle Control 1 Register
32
R/W
0400h
FFFE:CE08
ARM_IDLECT2
MPU Idle Control 2 Register
32
R/W
0100h
FFFE:CE0C
ARM_EWUPCT
MPU External Wakeup Control Register
32
R/W
003Fh
FFFE:CE10
ARM_RSTCT1
MPU Reset Control 1 Register
32
R/W
0000h
FFFE:CE14
ARM_RSTCT2
MPU Reset Control 2 Register
32
R/W
0000h
FFFE:CE18
ARM_SYSST
MPU System Status Register
32
R/W
0038h
FFFE:CE1C
ARM_CKOUT1
MPU Clock Out Definition Register 1
32
R/W
0015h
FFFE:CE20
ARM_CKOUT2
MPU Clock Out Definition Register 2
32
R/W
0000h
FFFE:CE24
ARM_IDLECT3
MPU Idle Enable Control Register 3
32
R/W
0015h