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參數(shù)資料
| 型號(hào)： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁(yè)數(shù)： | 87/145頁(yè) |
| 文件大小： | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
46
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
NOTE: 1. Values are only cleared by SB_POWEROK (cold-boot) to preserved state in case of a catastrophic event. Values
preserved during warm-boot.
2. Values are dependent upon core frequency. These values are good for 33 MHz only.
Slave Control (Device 7h, Function 1h)
ADDRESS: 8Ch-8Fh
SYMBOL: SMBCONT
BITS
DESCRIPTION
PROPERTIES
RESET
NOTES
31:24
SMB Slave Address. The I/O Controller SMB Slave interface
will respond on the SMB bus to this address. Although this
address contains 8 bits, only bits 7:1 are used for address
comparison. Bit 0 indicates Read/Write.
R/W
40h
1
23:16
SMB Slave Acknowledge Count. Programmable count for
SMB input capture window. This count determines where in
the valid data window the SMB_DATA line is sampled.
R/W
4Fh
1
15
SMS Enable. When set, the SMB slave is enabled. When clear,
the SMB slave will not respond on the SMB bus.
R/W
1
14:11
SMS Configuration Record Pointer Register.
0000 - PCI-LPC Bridge.
0001 - SMBus Controller function.
0010 - Micron Reserved.
0011 - IDE Controller function.
0100 - USB Controller function.
R/O
0000
10
Reserved
R/O
0
9
Upper bit of Timeout Counter.
R/W
0
1, 2
8
Micron Reserved.
R/O
0
7:1
Upper byte of Timeout Counter, Bit 9 and these bits make up
the Timeout Count that is used to determine if the SMB bus
should time-out. In the time-out case, the SMB Slave must get
off the bus to allow the SMB Master to generate a SMB stop.
For example, for an Upper count of 1F4h: the 1 is set in bit 9,
F4h is setup in 7:1.
R/W
1100101b
1, 2
0
Micron Reserved.
R/O
0
Power Management Capable Block Register (Device 7h, Function 1h)
ADDRESS: 90h-93h
SYMBOL: PWR_CAP
BITS
DESCRIPTION
PROPERTIES
RESET
NOTES
31
PME D3cold Supported.
R/WP
1
30
PME D3hot Supported.
R/WP
1
29
PME D2 Supported.
R/O
0
2
28
PME D1 Supported.
R/O
0
2
27
PME D0 Supported.
R/O
0
2
26
D2 Supported.
R/O
0
2
25
D1 Supported.
R/O
0
2
24:22
AUX Current.
R/O
0
2
21
Device Specific Implementation.
R/WP
0
1
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