參數(shù)資料
型號： MT8LLN22NCNE
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA316
封裝： 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù)： 141/145頁
文件大?。?/td> 2285K
代理商： MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
95
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
NOTE:
Register is standby powered and unaffected by SB_POWEROK or P_RST#. Reset only with RSMRST#.
General Purpose 0 Status
ADDRESS: ACPI_BASE + 14h
SYMBOL: GPSTS0
BITS
DESCRIPTION
PROPERTIES
RESET
15:10
Reserved.
R/O
0000b
9
GPI_STS VCORE. GPI VCORE Status. Set with an enabled General Purpose
input event occurred in ACPI_BASE + A0h. When enabled with GPI_EN
VCORE, a SCI, SMI#, or wake event will be generated.
R/WOTC
0
8
GPI_STS. GPI Status. Set with an enabled Standby General Purpose input
event occurred in ACPI_BASE + 54h or ACPI_BASE + 80h. When enabled
with GPI_EN, a SCI, SMI#, or wake event will be generated.
R/WOTC
0
7Reserved.
R/O
0
6
THRM_OVR_STS. Thermal Override Status. Set when H_THRM# is asserted
for 2 seconds and thermal clock throttling initiated. Remains cleared if
thermal clock throttling isn’t initiated. This bit generates an override
that starts throttling the CPU clock at the THRM_DTY cycle. When
enabled with THRM_OVR_EN, a SCI, SMI#, or wake event will be gener-
ated.
R/WOTC
00b
5
THRM_STS. Thermal Status. Set when H_THRM# asserted. Assertion level
is specified by THRM_POL bit. If the THRM_EN and THRM_STS bits are set
then a SCI, SMI#, or wake event will be generated.
R/WOTC
00b
4
Micron Reserved.
R/O
0
3
USB_STS. USB Status. Set when USB resume (connect, disconnect, or USB
resume) has occurred. If the USB_EN and USB_STS bits are set then a SCI,
SMI#, or wake event will be generated.
R/WOTC
0
2
SMB_STS. SMB Status. Set when a SMB wake event (ALERT) is detected.
Typically this is used as a PME for motherboard components.
R/WOTC
0
1
EXT_SMI_STS. External SMI Status. Set when a PWR_EXT_SMI# active
event is detected. Allowed to wake-up system in S1.
R/WOTC
0
PME_STS. PME Status. Set when P_PME# is asserted. If the PME_EN and
PME_STS bits are set then a SCI, SMI#, or wake event will be generated.
R/WOTC
0
General Purpose 0 Enable
ADDRESS: ACPI_BASE + 16h
SYMBOL: GPEN0
BITS
DESCRIPTION
PROPERTIES
RESET
15:10
Reserved.
R/O
0000b
9
GPI_EN VCORE. GPI VCORE Enable. When set, the corresponding event in
the GPSTS0 register will cause a SCI, SMI#, or wake event. When clear, no
SCI, SMI#, or wake event will be generated.
R/W
0
8
GPI_EN. GPI Enable. When set, the corresponding event in the GPSTS0
register will cause a SCI, SMI#, or wake event. When clear, no SCI, SMI#,
or wake event will be generated.
R/W
0
7Reserved.
R/O
0
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