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參數(shù)資料
| 型號(hào)： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁數(shù)： | 103/145頁 |
| 文件大?。?/td> | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
60
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Configuration Control Register (Device 7h, Function 2h)
ADDRESS: 68h-6Bh
SYMBOL: PWRMNGT_CTRL
BITS
DESCRIPTION
PROPERTIES
RESET
31:26
Reserved.
R/W
0
25
GPM Sequence. Must be set.
R/W
0
24
GPM prefetch flush enable. Must be set.
R/W
0
23
Enable Write Discard Timer. When set, a write request will be discarded
and retried if not responded to after 64K PCI clocks. When clear, the
write request will continue indefinitely until completed.
R/W
0
22
Enable Read Discard Timer. When set, a read request will be discarded
and retried if not responded to after 64K PCI clocks. When clear, the read
request will continue indefinitely until completed.
R/W
0
21
Delayed read enabled. When set, read transfers directed to the IDE con-
troller (down stream) may be performed as a PCI delayed read. When
clear, down stream delayed read operations will not be performed
R/W
0
20
Posting enabled. When set, writes operations directed to IDE will be
posted. When clear, no write posting occurs.
R/W
0
19
Fencing on delayed read completion. When set, delayed read data will
be sent to the PCI bus when posted memory writes that existed at the
time that the read data was returned have been flushed. When clear,
posted memory writes are not flushed.
R/W
0
18
Fencing enable, When set, read data is returned when the previous
posted memory writes which proceeded the read have been flushed.
When clear, the read data may be returned without flushing previous
writes.
R/W
0
17
Enable Empty Flagging. Must be set.
R/W
0
16
Prefetch Enable. When set, read requests from the IDE controller may be
prefetched. When clear, no prefetching occurs.
R/W
0
15:2
Reserved.
R/W
0
1
Capabilities Disable. When set, the Capabilities List functionality will be
disabled in registers 06h and 34h. When clear, Capabilities functionality
will return normal status in registers 06h and 34h.
R/W
0
Subsystem ID Write Protect Disable. When clear, Subsystem Vendor ID
and Subsystem ID registers will be write protected.
R/W
0
ATA Timing Control Register (Device 7h, Function 2h)
ADDRESS: 6Ch-6Fh
SYMBOL: ATA_TIM_CTRL
BITS
DESCRIPTION
PROPERTIES
RESET
31:12
Reserved.
R/O
0
11:8
Slew rate control for AD, CS0, CS1, IORD, IOWR, DACK, DRQ, IRQ.
R/W
0
7:4
Slew rate control for IOCHRDY pins.
R/W
0
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