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| 型號(hào)： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁(yè)數(shù)： | 34/145頁(yè) |
| 文件大?。?/td> | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
129
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Clock Throttling
Clock throttling is used to reduce the power con-
sumption of the processor. The I/O Controller issues
H_STPCLK# to throttle the processor. After a program-
mable period, H_STPCLK# is deasserted to allow the
processor to resume. The cycle is repeated to reduce
the average power of the processor, but also decreases
processor performance. There are two methods to
induce clock throttling. Manual throttling may be pro-
grammed using the THTL_DTY and THTL_EN fields.
Thermal override throttling occurs unconditionally
when H_THRM# goes active, the duty cycle is pro-
grammable through the THRM_DTY field.
Initiating Sleep State
Sleep states (S1, S3-S5) are initiated by setting the
SLP_EN bit or by asserting PWR_BUTTON#. The
proper Sleep State should be entered in the SLP_TYP
field
when
using
SLP_EN.
When
asserting
PWR_BUTTON#, the signal must be asserted for more
than four seconds to cause a power button override
event.
Causes of Wake Events
Wake events will cause an exit from sleep states.
Table 28 identifies causes and actions of certain wake
events.
Table 28
Causes of Wake Events
CAUSE
STATES CAN
WAKE FROM
HOW ENABLED
RTC Alarm
S1-S5
Set RTC_EN bit in PM1_EN Register
Power Button
S1-S5
Always enabled as Wake event
GPIO_VAUX[31:0]
S1-S5
GPE0_EN Register
GPIO_VCORE[15:0]
S1
GPE0_EN Register
USB
S1-S4
Set USB_EN bit in GPE0_EN Register
PME#
S1-S5
Set PME_EN bit in GPE0_EN Register.
ALERT#
S1-S4
SMB_EN in the GPE0 Register
Bus Master Request
(BM_STS)
S1
BM_RLD in the PM1_CNT Register
IRQ Resume
(IRQ_RSM_STS)
S1
IRQ_RSM_EN in the GLBEN Register
Global Power
Management Timer
S1
TMR_EN in the PM1_EN Register
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