參數(shù)資料
型號(hào)： MT8LLN22NCNE
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA316
封裝： 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù)： 68/145頁
文件大?。?/td> 2285K
代理商： MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
29
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Force Reset Register (Device 7h, Function 0h)
7:6
DMA Channel 3 LPC Cycle Size. Allowable values are:
00: 1 byte
01: 2 bytes
11: 4 bytes
R/W
00b
5:4
DMA Channel 2 LPC Cycle Size. Allowable values are:
00: 1 byte
01: 2 bytes
11: 4 bytes
R/W
00b
3:2
DMA Channel 1 LPC Cycle Size. Allowable values are:
00: 1 byte
01: 2 bytes
11: 4 bytes
R/W
00b
1:0
DMA Channel 0 LPC Cycle Size. Allowable values are:
00: 1 byte
01: 2 bytes
11: 4 bytes
R/W
00b
ADDRESS: 50h-53h
SYMBOL: FORC_RST
BITS
DESCRIPTION
PROPERTIES
RESET
31:9
Reserved
R/O
0
8
Force PCI reset. P_RST# is generated when a 1 is written to this field
W/O
0
7:1
Reserved.
R/O
0
Force INIT. Processor H_INIT# is generated when a 1 is written to this
field.
W/O
0
PCI INT[A] Interrupt Routing (Device 7h, Function 0h)
ADDRESS: 60h
SYMBOL: PCI_INTA
BITS
DESCRIPTION
PROPERTIES
RESET
7
Interrupt Routing Disable. When set, interrupt routing of the corre-
sponding P_INT is disabled and is not routed to the 8259. When clear,
The corresponding P_INT will be routed to one of the interrupts specified
in bits 3:0.
R/W
1
6:4
Reserved
R/W
0
DMA Control (Device 7h, Function 0h) (continued)
ADDRESS: 48h-4Bh
SYMBOL: DMA_CTRL
BITS
DESCRIPTION
PROPERTIES
RESET
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