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參數(shù)資料
| 型號(hào)： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁(yè)數(shù)： | 140/145頁(yè) |
| 文件大小： | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
94
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Level 3 Register
NOTE:
Register is standby powered and unaffected by SB_POWEROK or P_RST#. Reset only with RSMRST#.
Processor Clock Control Register
NOTE:
Register is standby powered and unaffected by SB_POWEROK or P_RST#. Reset only with RSMRST#.
ADDRESS: ACPI_BASE + 11h
SYMBOL: LVL3
BITS
DESCRIPTION
PROPERTIES
RESET
7:0
LVL3. Level 3 Power State Entry. Reads to this register will return zeros
and cause the CPU power management controller to enter C3 state.
Writes have no effect.
R/O
0
ADDRESS: ACPI_BASE + 12h
SYMBOL: P+CLK_CTRL
BITS
DESCRIPTION
PROPERTIES
RESET
15:12
Number of CPUs. This field is used to determine the number of CPUs in
the system. Stop Grant special cycles are issued by each CPU. The I/O con-
troller must account for all Stop Grants issued by each CPU before transi-
tioning to the Stop Grant or lower Power Management states.
R/W
0
11:10
Reserved.
R/O
0
9
THRM_THT_EN. THRM throttle enable. When set, H_STPCLK# will be
throttled when a THRM Event is sampled. When clear, H_STPCLK# will
not be throttling unless a THRM Override condition is sampled.
R/W
0
8
THTL_CNT_RST_SEL. Throttle Count Reset Selection. Wake Events and
Break Events can cause H_STPCLK# throttling to be deasserted early.
When throttling resumes, this bit is used to determine if the throttle
count is reset to the default count value or continued from the last count
value. When set, the default throttle count is used upon throttle resump-
tion. When clear, the last count value is used upon throttle resumption.
R/W
0
7Reserved.
R/W
0
6Reserved.
R/O
0
5
CC_STS. Clock Control Status. When set, I/O Controller clock control is
active. When clear, I/O Controller clock control is inactive.
R/O
0
4Reserved.
R/O
0
3Reserved.
R/O
0
2
SLEEP_EN. Sleep Enable (S1 state). Set enables H_SLEEP# signal assertion
when placed into LVL3 clock control. Disabled when clear.
R/W
0
1Reserved
R/O
0
CC_EN. Clock Control Enable. Set enables CPU clock control. This enables
reads to LVL2 and LVL3 registers to cause the I/O Controller to enter the
enabled clock mode.
R/W
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8LLN22NCNE-A | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET - Trays |
| MT8LLN22NCNE-A2 | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET AND MOTHERBOARD - Trays |
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