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參數資料
| 型號： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁數： | 65/145頁 |
| 文件大小： | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
26
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
18
Core Bus Posting Enable. When set, write transfers directed at the I/O
controller (down stream) will be posted. When clear, down stream
writes will not be posted.
R/W
0
17
Core Bus Delayed Read Enable. When set, read transfers directed to
the I/O controller (down stream) may be performed as a PCI delayed
read. When clear, down stream delayed read operations will not be
performed.
R/W
0
16
Serial IRQ Level Selection. Select the polarity of a level sensitive inter-
rupt on the LPC Serial IRQ input. When set, L_SERIRQ is active HIGH.
When clear, L_SERIRQ is active LOW.
R/W
0
15
Alternate Access Enable. When set, the state of certain registers may
be read/written by an alternate access port to restore the system by
power management software. When clear, the registers are inaccessi-
ble by the alternate access port.
R/W
0
14
Co-processor Error Function Enable. When set, H_FERR# is sampled.
When clear, H_FERR# is ignored.
R/W
0
13
Enable Read Discard Timer. When set, a read request will be discarded
and retried if not responded to after 64K PCI clocks. When clear, the
read request will continue indefinitely until completed.
R/W
0
12
Enable Write Discard Timer. When set, a write request will be discarded
and retried if not responded to after 64K PCI clocks. When clear, the
write request will continue indefinitely until completed.
R/W
0
11
Long Count Abort Enable. When set, a LPC cycle that is responded to
with a “Long Sync” LPC response exceeding 64K PCI clocks may be
aborted. When clear, the cycle will never be aborted.
R/W
0
10
Short Retry Enable. When set, a LPC cycle that is responded to with a
“Short Sync” LPC response may be retried if it exceeds the 8 clocks for
sync ready. When clear, the cycle will not be retried.
R/W
0
9
Fencing Delayed Reads on Completion Enable. When set, delayed read
data will be sent to the PCI bus when posted memory writes that
existed at the time that the read data was returned have been flushed.
When clear, posted memory writes are not flushed. Must be set.
R/W
0
8
Fencing Enable. When set, read data is returned when the previous
posted memory writes which proceeded the read have been flushed.
When clear, the read data may be returned without flushing previous
writes. Must be set.
R/W
0
7
DMA Subtractive Decode Enable. When set, DMA I/O addresses are
subtractively decoded by the I/O controller. When clear, DMA I/O
addresses are positively decoded by the I/O controller.
R/W
0
6
Real Time Clock Enable. When set, the RTC core logic is enabled. When
clear, the RTC core logic is disabled and inaccessible.
R/W
0
5
Programmable Interrupt Controller Enable. When set, the PIC core
logic is enabled. When clear, the PCI core logic is disabled and
inaccessible.
R/W
0
Core Bus Control (Device 7h, Function 0h) (continued)
ADDRESS: 40h-43h
SYMBOL: BUS_CTRL
BITS
DESCRIPTION
PROPERTIES
RESET
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