參數(shù)資料
型號： MT8LLN22NCNE
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA316
封裝： 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù)： 64/145頁
文件大?。?/td> 2285K
代理商： MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
25
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Capabilities Pointer (Device 7h, Function 0h)
NOTE: 1. The Capabilities List enabled attribute is controlled by the capability disable bit (bit 30 of register 40h). When
this bit is set, the Capabilities list is disabled this field will return all zeros.
ADDRESS: 34h-38h
SYMBOL: CAP_PTR
BITS
DESCRIPTION
PROPERTIES
RESET
NOTES
31:8
Reserved.
R/O
0
7:0
Capabilities List Pointer.
R/O
90h
1
Core Bus Control (Device 7h, Function 0h)
ADDRESS: 40h-43h
SYMBOL: BUS_CTRL
BITS
DESCRIPTION
PROPERTIES
RESET
31
SMB Capabilities Disable. When set, the Capabilities List functionality
will be disabled in registers 06h and 34h of function 1. When clear,
Capabilities functionality will return normal status in registers 06h and
34h of function 1.
R/W
0
30
Capabilities Disable. When set, the Capabilities List functionality will be
disabled in registers 06h and 34h. When clear, Capabilities functionality
will return normal status in registers 06h and 34h.
R/W
0
29
Write retry Read Holding. When set, a write matching an already com-
pleted delayed read will be retried until the delayed read has been
completed on the PCI bus. When clear, the write may be accepted.
R/W
0
28
PIT Timer 1 Edge bit. Must be set.
R/W
0
27
Timer 2 Mode 2 PIT bit. Must be set.
R/W
0
26
Enable target read on master empty. Must be set.
R/W
0
25
Enable read/write of subsystem ID and subsystem vendor ID register
2Ch. When set writes to these registers is enabled. When clear, these
registers are write protected.
R/W
0
24
LPC I/O delayed read enable. When set, PCI delayed reads to the LPC
I/O space are enabled. When clear, PCI delayed reads to the I/O space is
disabled.
R/W
0
23
LPC memory delayed read enable. When set, PCI delayed reads to the
LPC memory space are enabled. When clear, PCI delayed reads to the
memory space are disabled.
R/W
0
22
LPC I/O delayed write enable. When set, I/O writes are treated in the
same manner as PCI delayed reads. When clear, I/O writes are treated
normally.
R/W
0
21
LPC memory delayed write enable. When set, memory writes are
treated in the same manner as PCI delayed reads. When clear, memory
writes are treated normally.
R/W
0
20
LPC I/O Posting Enable. When set, I/O write operations directed to LPC
will be posted. When clear, no I/O write posting occurs.
R/W
0
19
LPC memory posting enable. When set, memory write operations
directed to LPC will be posted. When clear, no memory write posting
occurs.
R/W
0
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