參數(shù)資料
型號： MT8LLN22NCNE
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA316
封裝： 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù)： 53/145頁
文件大?。?/td> 2285K
代理商： MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
15
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
IDE_PRI_IOWR#
IDE_SEC_IOWR#
OVDD3.3
Primary and Secondary Disk I/O Write signals are used in different ways
depending on the mode and type of transfer. For PIO and Non-Ultra
DAM transfers these signals indicate to the IDE device that it may latch
data form the IDE data lines. The IDE device latches the data on the
deassertion (rising) edge of IDE_PRI_IOWR# or IDE_SEC_IOWR#. The
IDE device is selected by the ATA chip selects or the IDE DMA acknowl-
edge. For Ultra DMA writes to disk these signals are the data write
strobes. In Ultra DMA mode I/O Controller uses these signals to termi-
nate a data burst.
IDE_PRI_IRQ
IDE_SEC_IRQ
IVDD3.3
Primary and Secondary IDE interrupt inputs are connected to the IDE
drives. IRQ14 is used by the drives connected to the primary controller
and IRQ15 is used by the drives connected to the secondary controller.
IDE_SH_A[2:0]
O
VDD3.3
IDE Address signals are used to indicate which byte in either the ATA
command block or control block is being addressed. Gets routed from
the I/O Controller to both the primary and secondary IDE connectors.
IDE_SH_CS[1:0]#
O
VDD3.3
IDE Chip Select 0 is the primary port chip select 1xx. IDE_SH_CS0# is
driven before the read or write command signals are asserted to satisfy
the disk chip select setup time of the IDE drives. Gets routed from the I/
O Controller to both the primary and secondary IDE connectors.
IDE_ROM_CE#
O
Reserved
IDE (continued)
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
Interrupt Signals
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
P_INT#[D:A]
I
VDD3.3
PCI Interrupt Request. P_INT#[D:A] are used by PCI devices to request
attention from their drivers. P_INT#[D:A] lines can be shared between PCI
devices by wired “OR.”
P_INT#[15:0]
I
Extended PCI interrupt Request Lines. Same functionality as P_INT#[D:A].
General Purpose Signals
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
GPIO[21]
I/O
Standby Shared with CPUSTP#
GPIO[20]
I/O
Standby Shared with PCISTP#
GPIO[19]
I/O
Standby Shared with DCSTP#
GPIO[18]
I/O
Standby Shared with APIC_D[1]
GPIO[17]
I/O
Standby Shared with APIC_D[0]
GPIO[16]
I/O
Standby Shared with SMB_CLK.
GPIO[15]
I/O
Standby Shared with SMB_DATA.
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