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參數(shù)資料
| 型號： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁數(shù)： | 31/145頁 |
| 文件大小： | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
126
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Real Time Clock
The
I/O
Controller
integrates
a
Motorola
(MC146818A compatible Real Time Clock (RTC) with
256 bytes of battery-backed RAM. The real-time clock
performs two key functions, keeping track of the time
of day and storing system data, even when the system
is powered down. The RTC operates on a 32.768 KHz
crystal and a separate 3V lithium battery that provides
up to seven years of protection. The RTC also supports
two lockable memory ranges. By setting bits in the
configuration space, two 8-byte ranges can be locked
to read and write accesses. This prevents unauthorized
reading of passwords or other system security infor-
mation. The RTC also supports a date alarm that
allows for scheduling a wake up event up to 30 days in
advance. The month alarm provides for alarms within
the next year.
Power Management
The power management functions of the I/O Con-
troller include enhanced clock control, local and glo-
bal monitoring support for 33 individual devices, and
various low power (suspend) states (e.g., Suspend-to-
DRAM and Suspend-to-Disk). A hardware-based ther-
mal management circuit permits software-indepen-
dent entrance to low-power states. The I/O Controller
contains full support for the Advanced Configuration
and Power Interface (ACPI) Specification. The CPU
power management unit allows for multi-processor
clock control supports of processor stop-grant and
sleep power management states.
Sleep State Overview
The I/O Controller directly supports different sleep
states (S1-S5), setting the SLP_EN enters Sleep states
bit, or due to a Power Button Override. The entry to the
Sleep states are based on several assumptions:
Entry to a Cx state is mutually exclusive with entry
to a Sleep state. This is because the processor can
only perform one register access at a time. A request
to sleep always has higher priority than throttling.
Prior to setting the SLP_EN bit, the software turns
off processor-controlled throttling. Note that ther-
mal throttling cannot be disabled, but setting the
SLP_EN bit disables thermal throttling (since S1-S5
Sleep State has higher priority).
Upon exit from the I/O Controller-controlled Sleep
states (S1, S3, S4, S5), the RSM_STS bit is set to 1.
System Power States
Table 26 identifies the power states that may be
used in systems employing the I/O Controller. The
state names generally correspond to states defined by
the ACPI specification. Table 27 identifies the power
state transition rules.
14
IRQ[14]
High Edge
IDE/LPC interrupt
13
IRQ[13]
High Edge
Processor interrupt
12
IRQ[12]
High Edge
Mouse interrupt
11
IRQ[11]
High Edge
LPC interrupt
10
IRQ[10]
High Edge
LPC interrupt
09
IRQ[09]
High Edge
LPC interrupt
08
IRQ[08]
High Edge
RTC interrupt
07
IRQ[07]
High Edge
LPC interrupt
06
IRQ[06]
High Edge
LPC interrupt
05
IRQ[05]
High Edge
LPC interrupt
04
IRQ[04]
High Edge
LPC interrupt
03
IRQ[03]
High Edge
LPC interrupt
02
IRQ[02]
High Edge
Timer/Counter interrupt
01
IRQ[01]
High Edge
Keyboard interrupt
00
IRQ[00]
High Edge
Processor interrupt
Table 25
APIC Interrupt Mapping (continued)
APIC IRQ INPUT
ROUTING
TRIGGERED
DESCRIPTION
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相關代理商/技術參數(shù) |
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|---|---|
| MT8LLN22NCNE-A | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET - Trays |
| MT8LLN22NCNE-A2 | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET AND MOTHERBOARD - Trays |
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