參數資料
型號: MT8LLN22NCNE
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA316
封裝: 27 X 27 MM, PLASTIC, BGA-316
文件頁數: 72/145頁
文件大小: 2285K
代理商: MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
32
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Power Management Base Address (Device 7h, Function 0h)
3:0
Interrupt Routing. SCI interrupts will be routed to the following inter-
rupt. Values not shown are reserved.
0011: IRQ3
0100: IRQ4
0101: IRQ5
0110: IRQ6
0111: IRQ7
1001: IRQ9
1010: IRQ10
1011: IRQ11
1100: IRQ12
1110: IRQ14
1111: IRQ15
R/W
0
ADDRESS: 68h-69h
SYMBOL: ACPI_BASE
BITS
DESCRIPTION
PROPERTIES
RESET
15:8
Base Address for the ACPI and GPIO I/O space. Any non-zero value is con-
sidered an enable. Allows for 256 Bytes of I/O space to be mapped along
256 byte boundaries.
R/W
0
7:2
Reserved.
R/O
0
1Reserved.
R/O
0
Space type. Indicates I/O space.
R/O
1
SCI Interrupt Routing (Device 7h, Function 0h) (continued)
ADDRESS: 66h
SYMBOL: SCI_INT_ROUT
BITS
DESCRIPTION
PROPERTIES
RESET
Extended Enable (Device 7h, Function 0h)
ADDRESS: 6Ah
SYMBOL: EXT_EN
BITS
DESCRIPTION
PROPERTIES
RESET
7
GPM Sequence. Must be set.
R/W
0
6
GPM prefetch flush enable. Must be set.
R/W
0
5
APIC Flush Enable. When set, the APIC will wait until an
APIC_FLUSH_ACK# has been detected before issuing a packet on the
APIC bus. When clear, APIC_FLUSH_ACK# is ignored.
R/W
0
4
Micron Reserved
R/W
0
3
LPC Target Enabled. When set, LPC bus masters may perform upstream
transactions. When clear, the I/O controller will ignore LPC bus master
requests.
R/W
0
2
APIC enabled. When set, memory cycles directed to the I/O APIC memory
space are enabled for address decode. When clear, memory cycles
directed to the I/O APIC memory space are ignored.
R/W
0
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