- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98045 > MT8LLN22NCNE PCI BUS CONTROLLER, PBGA316 PDF資料下載
參數(shù)資料
| 型號(hào)： | MT8LLN22NCNE |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁(yè)數(shù)： | 46/145頁(yè) |
| 文件大?。?/td> | 2285K |
| 代理商： | MT8LLN22NCNE |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)當(dāng)前第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
14
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
APIC_FLUSH_ACK
I
9DD
APIC Flush Acknowledge. Connected to the Host Controller APIC Flush
Request pin to acknowledge that write buffers are flushed to memory.
APIC_FLUSH_REQ
O
9DD
APIC Flush Request. Connected to the Host Controller APIC Flush
Request pin to request that write buffers must be flushed to
memory.
APIC Signals
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
IDE
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
IDE_PRI_D [15:0]
IDE_SEC_D [15:0]
I/O
VDD3.3
The Primary and Secondary IDE channels each have a 16-bit data path.
These signals connect to the corresponding signals on the IDE
connector.
IDE_PRI_IORD#
IDE_SEC_IORD#
OVDD3.3
Primary and Secondary I/O Read signals are used in different ways
depending on the mode and type of transfer. For PIO and Non-Ultra
DMA transfers these signals inform the IDE device that it may drive
data onto the primary or secondary IDE data lines. The I/O Controller
latches the data on the deassertion (rising) edge of IDE_PRI_IORD# or
IDE_SEC_IORD#. The IDE device is selected by the ATA chip selects or
the IDE DMA acknowledge. For Ultra DMA writes to disk these signals
are the data write strobes. When writing to the disk I/O Controller
drives valid data onto the bus on rising and falling edges of
IDE_PRI_IORD#, IDE_SEC_IORD#. For Ultra DMA reads form the disk
these signals indicate DMA ready. When reading from the disk I/O Con-
troller will deassert IDE_PRI_IORD#, IDE_SEC_IORD# to pause burst data
transfers.
IDE_PRI_IOCHRDY
IDE_SEC_IOCHRDY
IVDD3.3
Primary and Secondary I/O channel ready signals are used in different
ways depending on the mode and type of transfer. For PIO mode trans-
fers these signals are used to add wait states to a transfer. For Ultra
DMA reads from the disk I/O Controller latches data on the rising and
falling edges of these signals. For Ultra DMA writes to disk these sig-
nals are used by the IDE device to pause burst data transfers.
IDE_PRI_DACK#
IDE_SEI_DACK#
OVDD3.3
Primary and Secondary IDE Device DMA Acknowledge signals are
driven by the I/O Controller when it is ready to fill a previous request
on IDE_PRI_DRQ or IDE_SEC_DRQ from the IDE device.
IDE_PRI_DRQ
IDE_SEC_DRQ
IVDD3.3
Primary and Secondary IDE Device DMA Request signals are driven by
the IDE device to request the transfer of DMA data.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MTB10N40ET4 | 10 A, 400 V, 0.55 ohm, N-CHANNEL, Si, POWER, MOSFET |
| MTB15N06V | 15 A, 60 V, 0.12 ohm, N-CHANNEL, Si, POWER, MOSFET |
| MTB15N06VT4 | 15 A, 60 V, 0.12 ohm, N-CHANNEL, Si, POWER, MOSFET |
| MTB16N25E | 16 A, 250 V, 0.25 ohm, N-CHANNEL, Si, POWER, MOSFET |
| MTB16N25ET4 | 16 A, 250 V, 0.25 ohm, N-CHANNEL, Si, POWER, MOSFET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8LLN22NCNE-A | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET - Trays |
| MT8LLN22NCNE-A2 | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET AND MOTHERBOARD - Trays |
| MT8LSDF3264WG-133D1 | 制造商:Micron Technology Inc 功能描述:256MB 32MX64 SYNCH DRAM MODULE MICRO DIMM 3.3V - Trays |
| MT8LSDT1664 | 制造商:Micron Technology Inc 功能描述:128MB 16MX64 SDRAM MODULE PBF DIMM 3.3V - Trays |
| MT8LSDT1664AG-10EB1 | 制造商:Micron Technology Inc 功能描述:DRAM MOD SDRAM 1GBIT 168UDIMM - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。