參數(shù)資料
型號： MT8LLN22NCNE
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA316
封裝： 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù)： 143/145頁
文件大小： 2285K
代理商： MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
97
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
NOTE:
Register is standby powered and unaffected by SB_POWEROK or P_RST#. Reset only with RSMRST#.
6:4
USB Aux. Current requirements. Corresponds to the value to be seen in
the USB PCI power management capability registers.
R/W
0
3
Enable USB PME generation in D0 state. Corresponds to the value to be
seen in the USB PCI power management capability registers.
R/W
0
2
Enable USB D2 state support. Corresponds to the value to be seen in the
USB PCI power management capability registers.
R/W
0
1
Enable USB D1 state support. Corresponds to the value to be seen in the
USB PCI power management capability registers.
R/W
0
Enable USB PCI-PM capabilities list. When this bit is set the PCI power
management capabilities registers will be enabled in USB PCI configura-
tion space. This will set the capabilities flag and unmask the capabilities
pointer.
R/W
0
Global Status Register
ADDRESS: ACPI_BASE + 20h
SYMBOL: GLBSTS
BITS
DESCRIPTION
PROPERTIES
RESET
15:12
Reserved.
R/W
0000b
11
IRQ_RSM_STS. IRQ Resume Status. Set indicates that the system may be
resume from POS due to interrupt assertion from IRQ [15:3,1]. When set
with IRQ_RSM_EN the system will wake from the S1 state and WAK_STS
will be set.
R/WOTC
0
10
EXT_SMI_STS. External SMI Status. When set, indicates the
PWR_EXT_SMI# signal was asserted. When set with EXT_SMI_EN set an
SMI will be signaled to the processor through the EOSMI flag, provided
SMI_EN is set.
R/WOTC
0
9
LEGACY_USB_STS. Legacy USB Status. When set, legacy keyboard/mouse
logic may generate an SMI. When set with LEGACY_USB_EN set an SMI
will be signaled to the processor through the EOSMI flag, provided
SMI_EN is set.
R/WOTC
0
8
SECOND_STS. Will set once per second. When set with SECOND_EN set an
SMI will be signaled to the processor through the EOSMI flag, provided
SMI_EN is set.
R/WOTC
0
7
GP_STS0. GP Status 0. When set, indicates that one of the status bits in
GPSTS0 (14h) register is set. Resetting all the bits in the GPSTS register
will clear this bit. When set with GPE0_EN set an SMI will be signaled to
the processor through the EOSMI flag, provided SMI_EN is set.
R/O
0
6
PM1_STS. PM1 Status. When set, indicates that one of the status bits in
the PM1_STS (00h) register is set. Resetting all the bits in the PMSTS reg-
ister clears this bit. When set with PM1_EN set an SMI will be signaled to
the processor through the EOSMI flag, provided SMI_EN is set.
R/O
0
USB Capabilities Control (continued)
ADDRESS: ACPI_BASE + 1Ch
SYMBOL: USB_CAP
BITS
DESCRIPTION
PROPERTIES
RESET
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