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參數(shù)資料
| 型號(hào)： | MT8LLN22NCNE |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁(yè)數(shù)： | 13/145頁(yè) |
| 文件大?。?/td> | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
11
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
P_C_BE#
[3:0]
I/O
VDD3.3
PCI Bus Command and Byte Enable are multiplexed on the same pins. Dur-
ing the address phase of a transaction P_C_BE#[3:0] define the bus com-
mand. During the data phase, P_C_BE#[3:0] are used as byte enables.
C/BE [3:0]# COMMAND TYPE
0000 INTERRUPT ACKNOWLEDGE
0001 SPECIAL CYCLE
0010 I/O READ
0011 I/O WRITE
0110 MEMORY READ
0111 MEMORY WRITE
1010 CONFIGURATION READ
1011 CONFIGURATION WRITE
1100 MEMORY READ MULTIPLE
1101 DUAL ADDRESS CYCLE
1110 MEMORY READ LINE
1111 MEMORY WRITE AND INVALIDATE
All command encodings not shown are reserved. The I/O Controller does
not decode reserved values, and therefore will not respond if a PCI master
generates a cycle using one of the reserved values.
P_DEVSEL#
I/O
VDD3.3
Device Select. P_DEVSEL# is actively driven by a PCI target when it has
decoded its address making it the target of the current access. When the I/
O Controller is the PCI master P_DEVSEL# is sampled to determine if the PCI
target is responded to. The I/O Controller will drive this signal when it
decodes the address and determines it is the target of the current transac-
tion. The I/O controller will assert P_DEVSEL, accept, and forward to the
LPC bus any and all unclaimed memory or I/O cycles as a subtractive decode
device when subtractive decode is enabled.
P_FRAME#
I/O
VDD3.3
Cycle Frame is driven by the current PCI master to indicate the beginning
and duration of an access. When the I/O Controller is the PCI master it will
drive P_FRAME# to initiate a PCI transaction. When the I/O Controller is the
PCI target P_FRAME# is sampled.
P_GNT_1#
I
VDD3.3
PCI Acknowledge 1. Primary arbitration grant. An active low assertion indi-
cates that the I/O Controller has been granted use of the PCI bus.
P_GNT_2#
I
VDD3.3
PCI Acknowledge 2. Secondary arbitration grant. Optional dedicated PCI
acknowledge for internal IDE and USB, with P_GNT_1# dedicated to the
LPC bridge.
P_IDSEL
I
VDD3.3
Initialization device select. P_IDSEL is used as a chip select during PCI con-
figuration read and write cycles.
P_IRDY#
I/O
VDD3.3
PCI Initiator Ready. P_IRDY# indicates the PCI masters ability to complete
the current data transaction.
P_M66EN
I
VDD3.3
Reserved. Tied LOW.
P_PAR
I/O
VDD3.3
Calculated/Checked Parity. P_PAR is used to create even parity across
P_AD[31:0] and P_C_BE#[3:0]. P_PAR is driven by whomever drove the
P_AD/P_C_BE bus on the previous cycle.
PCI Signal Descriptions (continued)
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
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| MTB15N06VT4 | 15 A, 60 V, 0.12 ohm, N-CHANNEL, Si, POWER, MOSFET |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8LLN22NCNE-A | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET - Trays |
| MT8LLN22NCNE-A2 | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET AND MOTHERBOARD - Trays |
| MT8LSDF3264WG-133D1 | 制造商:Micron Technology Inc 功能描述:256MB 32MX64 SYNCH DRAM MODULE MICRO DIMM 3.3V - Trays |
| MT8LSDT1664 | 制造商:Micron Technology Inc 功能描述:128MB 16MX64 SDRAM MODULE PBF DIMM 3.3V - Trays |
| MT8LSDT1664AG-10EB1 | 制造商:Micron Technology Inc 功能描述:DRAM MOD SDRAM 1GBIT 168UDIMM - Trays |
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