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參數(shù)資料
| 型號： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁數(shù)： | 116/145頁 |
| 文件大?。?/td> | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
72
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
DMA Channel [0-7] Base and Current Count Register
DMA Channel [0-3, 5-7] Low Page Address Register
ADDRESS: 01h
SYMBOL: DMABASE_CC
ADDRESS: 03h
ADDRESS: 05h
ADDRESS: 07h
ADDRESS: C2h
ADDRESS: C6h
ADDRESS: CAh
ADDRESS: CEh
DMA1 CHANNEL 0
DMA1 CHANNEL 1
DMA1 CHANNEL 2
DMA1 CHANNEL 3
DMA2 CHANNEL 4
DMA2 CHANNEL 5
DMA2 CHANNEL 6
DMA2 CHANNEL 7
BITS
DESCRIPTION
PROPERTIES
RESET
7:0
This 8-bit access port is used to access the 16-bit Current (Base) Count for
Channel. During WRITE operations, the value is stored in the Base Count
register and copied to the Current Count Register. During READs, the
value from the Current Count register is returned.
The Current Count register holds the remaining number of transfers to
occur (either byte transfers for Channels 0-3, or word transfers for Chan-
nels 5-7) plus 1. The register decrements after each transfer. The register
rolling over from 0 to FFFFh indicates the terminal count has been
reached, and the transfer is complete.
Reads and Writes to this register are done on a successive byte basis, with
the Clear Master Byte Pointer Flag (Register 0Ch for DMA1, Register D8h
for DMA2) in control of resetting the toggle to the least significant byte.
The low byte should be accessed first.
R/W
0
ADDRESS: 87h
SYMBOL: DMAMEM_LP
ADDRESS: 83h
ADDRESS: 81h
ADDRESS: 82h
ADDRESS: 8Bh
ADDRESS: 89h
ADDRESS: 8Ah
DMA1 CHANNEL 0
DMA1 CHANNEL 1
DMA1 CHANNEL 2
DMA1 CHANNEL 3
DMA2 CHANNEL 5
DMA2 CHANNEL 6
DMA2 CHANNEL 7
BITS
DESCRIPTION
PROPERTIES
RESET
7:0
Corresponds to the low page address [23:16] that the channel is to move
the data from/to. The DMA Current Address register provides the other
16 address bits to form the 24-bit address. This register remains static
throughout the transfer.
R/W
0
DMA Command Register
ADDRESS: 08h
SYMBOL: DMACMD
ADDRESS: D0h
DMA1
DMA2
BITS
DESCRIPTION
PROPERTIES
RESET
7:5
Reserved.
W/O
0
4
DMA Arbitration Priority. Each DMA channel group is assigned fixed or
rotating arbitration priority. When set, the DMA arbitration priority is
rotating. When clear, the DMA arbitration priority is fixed.
W/O
0
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