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參數(shù)資料
| 型號(hào)： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁數(shù)： | 29/145頁 |
| 文件大?。?/td> | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
124
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
DMA Controller
The legacy DMA Controller integrated in the I/O
Controller performs the functionality of two 8237 DMA
controllers used in legacy systems. The I/O Controller
supports DMA to the LPC bus. Single, Demand, Verify,
and Increment modes are supported on the LPC inter-
face. Channels 0-3 are 8-bit channels, and channels 5-
7 are 16-bit channels. Channel 4 is reserved as a
generic bus master request. The DMA controller has
fixed I/O ranges for compatibility purposes. Devices
on the LPC bus request service of a DMA channel
through the LDRQ pins. PC/PCI type DMA transfers
are not supported.
Programmable Interval Timers
The I/O Controller integrates three legacy Program-
mable Interval Timers (PIC) which perform the func-
tionality of three 8254 timers and have fixed uses. Each
timer/counter operates off of a 1.193 MHz frequency,
so each counter period is 838ns.
Timer/Counter 0, System Timer
Timer/Counter 0 functions as the system timer by
controlling the state of IRQ[0] and is generally pro-
grammed for Mode 3 operation. The counter generates
a square wave with a period equal to the product of the
counter period, and the initial count value. The
counter is decremented by one every two counter peri-
ods. Each time the counter value reaches zero, the
value of IRQ[0] is negated, producing a square wave.
Timer/Counter 1, Refresh Request
Signal
Timer/Counter 1 provides the legacy Refresh
Request signal and is generally programmed for Mode
2 operation. The legacy Refresh Request signal is used
internally by the I/O Controller.
Timer/Counter 2, Speaker Tone
Timer/Counter 2 provides the speaker tone and is
generally programmed for Mode 3 operation. The
counter provides a speaker frequency that is equal to
the 1.193 MHz counter frequency divided by the initial
count value. The speaker tone is enabled via port 61h.
Programmable Interrupt Controllers
The I/O Controller integrates two Programmable
Interrupt Controllers (PIC) which perform the func-
tionality of two legacy 8259 interrupt controllers. The
interrupts supported include legacy device interrupts,
PCI-based interrupts. The slave 8259 is cascaded into
the master 8259 through master interrupt input 2.
Table 24 identifies the typical source and function of
each IRQ.
Table 24
IRQ Mapping
8259 INTERRUPT INPUT
INTERRUPT SOURCE
DESCRIPTION
Master 0
Internal
Timer/Counter 0 output
Master 1
Keyboard
IRQ[1] via L_SERIRQ, or legacy USB
Master 2
Internal
Slave controller INTR output
Master 3
Serial Port A
IRQ[3] via L_SERIRQ
Master 4
Serial Port B
IRQ[4] via L_SERIRQ
Master 5
Parallel Port/Generic
IRQ[5] via L_SERIRQ
Master 6
Floppy Disk
IRQ[6] via L_SERIRQ
Master 7
Parallel Port/Generic
IRQ[7] via L_SERIRQ
Slave 0
Internal
Real Time Clock
Slave 1
Generic
IRQ[9] via L_SERIRQ
Slave 2
Generic
IRQ[10] via L_SERIRQ
Slave 3
Generic
IRQ[11] via L_SERIRQ
Slave 4
PS/2 Mouse
IRQ[12] via L_SERIRQ, or legacy USB
Slave 5
Internal
H_FERR# assertion
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