參數(shù)資料
型號(hào)： MT8LLN22NCNE
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA316
封裝： 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù)： 110/145頁
文件大?。?/td> 2285K
代理商： MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
67
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
NOTE: 1. Values are only cleared by RSMRST# or a loss of standby power.
Power Management Control/Status Register (Device 7h, Function 3h)
ADDRESS: 64h-67h
SYMBOL: PWR_CTRL_STS
BITS
DESCRIPTION
PROPERTIES
RESET
NOTES
31:16
Reserved.
R/O
00000000h
15
PME_STS. Set when an USB resume event occurs on the USB
interface.
R/WOTC
00
1
14:9
Reserved.
R/O
00
8
PME_EN. When set, a P_PME# will be driven when PME_STS
is set
R/W
00
1
7:2
Reserved.
R/O
00
1:0
Power State. Can only be programmed to 0 and 3. Power
States 1 and 2 are enabled via D2 Supported and D1
Supported.
R/W
00
Configuration Control Register (Device 7h, Function 3h)
ADDRESS: 68h-6Bh
SYMBOL: CONF_CTRL
BITS
DESCRIPTION
PROPERTIES
RESET
31:26
Reserved.
R/W
00000000h
25
GPM Sequence. Must be set.
R/W
0
24
GPM prefetch flush enable. Must be set.
R/W
0
23
Enable Write Discard Timer. When set, a write request will be discarded
and retried if not responded to after 64K PCI clocks. When clear, the
write request will continue indefinitely until completed.
R/W
0
22
Enable Read Discard Timer. When set, a read request will be discarded
and retried if not responded to after 64K PCI clocks. When clear, the
read request will continue indefinitely until completed.
R/W
0
21
Delayed read enabled. When set, read transfers directed to the USB
controller (down stream) may be performed as a PCI delayed read.
When clear, down stream delayed read operations will not be per-
formed
R/W
0
20
Posting enabled. When set, writes operations directed to USB will be
posted. When clear, no write posting occurs.
R/W
0
19
Fencing on delayed read completion. When set, delayed read data will
be sent to the PCI bus when posted memory writes that existed at the
time that the read data was returned have been flushed. When clear,
posted memory writes are not flushed.
R/W
0
18
Fencing enable, When set, read data is returned when the previous
posted memory writes which proceeded the read have been flushed.
When clear, the read data may be returned without flushing previous
writes.
R/W
0
17
Enable Empty Flagging. Must be set.
R/W
0
16
Prefetch Enable. When set, read requests from the USB controller may
be prefetched. When clear, no prefetching occurs.
R/W
0
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