參數資料
型號: MT8LLN22NCNE
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA316
封裝: 27 X 27 MM, PLASTIC, BGA-316
文件頁數: 122/145頁
文件大?。?/td> 2285K
代理商: MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
78
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Read Back Command
COUNTER LATCH Command
Interrupt Controller (PIC) I/O
Register Set
The I/O Controller provides an interrupt controller
that is compatible with the functionality found in two
8259 interrupt controllers. The two interrupt control-
lers are cascaded so that 14 external and two internal
interrupts are possible. The external interrupts are
accessible through the PCI interrupt signals or via the
serial IRQ interface. Table 10 summarizes the PIC I/O
register set.
ADDRESS: 43h
SYMBOL: RDBK_CMD
BITS
DESCRIPTION
PROPERTIES
RESET
7:6
READ BACK Command. This field must be 11 to select the READ BACK
Command.
W/O
N/A
5
Latch Count. When set, current count of the selected counter will not be
latched. When clear, current count will be latched.
W/O
N/A
4
Latch Status. When set, counter status of the selected counter will not be
latched. When clear, counter status is latched.
W/O
N/A
3
Counter 2 Select.
W/O
N/A
2
Counter 1 Select.
W/O
N/A
1
Counter 0 Select.
W/O
N/A
0
Reserved. Must be 0.
W/O
N/A
ADDRESS: 43h
SYMBOL: LTCH_CMD
BITS
DESCRIPTION
PROPERTIES
RESET
7:6
Counter select. This field selects the counter the control word will act
upon. If this field is 11, then the write is interpreted as a Read Back Com-
mand.
00: Counter 0 select
01: Counter 1 select
10: Counter 2 select
W/O
N/A
5:4
COUNTER LATCH Command. This field must be 00 to select the COUNTER
LATCH Command.
W/O
N/A
3:0
Reserved. Must be 0.
W/O
N/A
Table 10
PIC I/O Register Set
ADDRESS
ALIAS
REGISTER
0020h
0024h,
0028h,
002Ch,
0030h,
0034h,
0038h
003Ch
Primary PIC ICW1 Initialization Command Word 1
Primary PCI OCW2 Operational Control Word 2
Primary PCI OCW3 Operational Control Word 3
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