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參數(shù)資料
| 型號： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁數(shù)： | 124/145頁 |
| 文件大?。?/td> | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
8
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
PCI Interface
The I/O Controller interfaces to the memory and
processor subsystem via an industry standard PCI bus.
The interface supports ... 2 lines of write data, for each
internal function.. The interface supports prefetching
of up to three lines of read data, and may post up to
two lines of write data. The PCI interface may be used
in systems that support more than 4GB of memory
space, although none of the integrated device operates
outside the 4GB memory space (the I/O controller will
not perform dual address cycles).
LPC Interface
The I/O Controller implements a Low Pin Count
(LPC) interface as described in the LPC 1.0 specifica-
tion. The Low Pin Count Bridge function in the I/O
Controller is controlled through the PCI register space.
The I/O Controller does not contain an ISA bus so the
LPC interface has been provided for connection to
Super I/O and Flash BIOS devices.
System Management Bus (SMBus)
Interface
The I/O Controller contains a SMBus Host Control-
ler that allows the processor to communicate with
SMBus slave devices. A SMBus slave interface allows
an external SMBus master to read and update internal
configuration registers of the I/O Controller.
USB Interface
The I/O Controller integrates a Universal Serial Bus
(USB) following the Open HCI standard. The USB
interface contains two integrated Root Hubs with four
USB ports, and USB Host Controller. Keyboard and
mouse legacy support are also included for DOS com-
patibility with USB devices.
IDE
The I/O Controller integrates two independent IDE
channels capable of supporting up to four hard drives,
CD-ROMs or ATAPI devices. Each device can be inde-
pendently programmed. In PIO mode the IDE inter-
face can transfer data up to 14 MB/s and in bus master
IDE mode data is transferred up to 100 MB/sec. The
IDE interface contains cache line FIFO depth per
channel for WRITE/READ cycles optimizing perfor-
mance.
Legacy South Bridge Functions
The I/O Controller integrates legacy devices such as
DMA Controller, Timer/Counters, and Programmable
Interrupt Controller. Additional legacy functions are
also provided to provide compatibility.
General Purpose I/O
The I/O Controller provides up to 41 General Pur-
pose I/O (GPIO) which may be used for control and
wake events. 16 dedicated GPIO reside on the standby
plane, 16 on the 3.3V plane, and another 9 GPIO are
shared with other signals.
Real Time Clock
The I/O Controller contains a real-time clock with
256 bytes of battery-backed RAM. The real-time clock
is used by the system to keep track of the time of day
and store system data while the system is running or
powered down. The RTC operates on a 32.768-kHz
crystal and a separate 3V lithium battery that provides
backup power while the system is powered down. The
RTC also supports two lockable memory ranges. By
setting bits in the configuration space, two 8-byte
ranges can be locked to read and write accesses. This
prevents unauthorized reading of passwords or other
system security information. The RTC also supports a
date alarm that allows for scheduling a wake up event
up to 30 days in advance. The month alarm provides
for alarms within the next year.
APIC
The I/O Controller can support up to 40 interrupts
through the APIC interface.
TERMINOLOGY
Host
Term used synonymously with the
processor.
North Bridge
The system controller that interfaces
to the host processor and main
memory.
POS
Power On Suspend.
South Bridge
The I/O controller that interfaces to
a PCI and LPC buses.
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