參數(shù)資料
型號： MT8LLN22NCNE
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA316
封裝： 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù)： 32/145頁
文件大?。?/td> 2285K
代理商： MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
127
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Table 26
General Power States
POWER STATE
DESCRIPTION
G0/S0/C0
Full On. The processor is operating, individual devices may be shut down to con-
serve power. The I/O Controller may perform clock throttling using H_STPCLK# to
reduce processor power consumption. Clock throttling may be initiated by software
or by the H_THRM# input signal.
G0/S0/C1
Auto-halt. Processor has executed a HALT instruction and is no longer executing
code. Cache coherency is maintained.
G0/S0/C2
Stop-Grant. The H_STPCLK# signal is issued to the processor. The processor issues a
Stop-Grant special cycle, halts the instruction stream, and remains halted until the
H_STPCLK# signal deactivates. Cache coherency is maintained.
G0/S0/C3
Sleep. The H_STPCLK# signal is issued to the processor. The processor issues a Stop-
Grant special cycle, halts the instruction stream, and remains halted until the
H_STPCLK# signal deactivates. The H_SLEEP# signal is then issued to the processor.
Cache coherency is not maintained.
G1/S1
Power On Suspend. All interfaces in the system are assumed to be in an enforced
idle condition. The H_STPCLK# signal is issued to the processor. The processor issues
a Stop-Grant special cycle, halts the instruction stream, and remains halted until the
H_STPCLK# signal deactivates. The I/O controller may optionally issue the H_SLEEP#
signal for further processor power reduction. Cache coherency is maintained.
G1/S3
Suspend To RAM (STR). The system context resides in system DRAM. I/O Controller
deasserts PWR_ON#. The PWR_ON# signal controls the power to non-critical circuits.
Power is only retained to devices needed to wake from this sleeping state, as well as
to the memory. Memory remains valid, and refreshes continue. All clocks except RTC
are stopped.
G1/S4
Suspend To Disk (STD). The system context resides on disk. I/O Controller deasserts
PWR_ON# and SOFF#. The SOFF# shuts off the power to the memory subsystem. All
power is removed except for the logic required to resume.
G2/S5
Soft Off (SOFF). System context is lost. I/O Controller asserts PWR_ON# and SOFF#.
The SOFF# signal shuts off the power to the memory subsystem. All power is
removed except for logic required to reboot. A full boot is required when waking.
G3
Mechanical Off (MOFF). System context is lost. All power is removed except for that
operating the RTC.
Table 27
Power State Transition Rules
CURRENT STATE
NEXT STATE
TRANSITION EVENT
G0/S0/C0
G0/S0/C1
Processor HALT instruction.
G0/S0/C0
G0/S0/C2
Level 2 Read.
G0/S0/C0
G0/S0/C3
Level 3 Read.
G0/S0/C0
G1/S1, G1/S3, G1/S4,
G2/S5
SLP_EN bit set.
G0/S0/C0
G2/S5
Power Button Override.
G0/S0/C0
G3
Mechanical off or power failure.
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