參數(shù)資料
型號: MT8LLN22NCNE
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA316
封裝: 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù): 112/145頁
文件大?。?/td> 2285K
代理商: MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
69
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Fixed I/O Registers
Table 6 illustrates the fixed I/O decode ranges of the
I/O controller. If a PCI master targets one of these I/O
addresses, the I/O controller will positively decode the
address to access the register.
DMA Controller I/O Register Set
The I/O Controller integrates the functional equiva-
lent to two 8237 DMA controllers providing support for
seven independently programmable DMA channels.
Channels 0-3 are hard coded to 8-bit transfers and
channels 5-7 are hard coded to 16-bit transfers. Chan-
nel 4 cascades the second DMA controller to the first
and is not externally available. Table 8 summarizes the
DMA Controller I/O register set.
Table 7
Variable I/O Register Set
VARIABLE RANGE
DESCRIPTION
SIZE
(BYTES)
UNIT
ACPI_BASE
ACPI registers
256
ACPI
IDE_BAR0
IDE native mode registers
16
IDE
IDE_BAR1
IDE native mode registers
16
IDE
IDE_BAR2
IDE native mode registers
16
IDE
IDE_BAR3
IDE native mode registers
16
IDE
IDE_BAR4
IDE native mode registers
16
IDE
SMB_BASE
SMB registers
64
SMB
Table 8
DMA I/O Register Set
ADDRESS
REGISTER
0000h
DMA1 Channel 0 Base and Current Address.
0001h
DMA1 Channel 0 Base and Current Count.
0002h
DMA1 Channel 1 Base and Current Address.
0003h
DMA1 Channel 1 Base and Current Count.
0004h
DMA1 Channel 2 Base and Current Address.
0005h
DMA1 Channel 2 Base and Current Count.
0006h
DMA1 Channel 3 Base and Current Address.
0007h
DMA1 Channel 3 Base and Current Count.
0008h
DMA1 Channel 0-3 Command register (write only).
DMA1 Channel 0-3 Status register (read only).
0009h
Reserved.
000Ah
DMA1 Channel 0-3 Write Single Mask Register.
000Bh
DMA1 Channel 0-3 Channel Mode.
000Ch
DMA1 Channel 0-3 Clear Byte Pointer.
000Dh
DMA1 Channel 0-3 Master Clear.
000Eh
DMA1 Channel 0-3 Clear Mask.
000Fh
DMA1 Channel 0-3 Read/Write All Mask Bits.
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