參數(shù)資料
型號： MT8LLN22NCNE
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA316
封裝： 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù)： 2/145頁
文件大?。?/td> 2285K
代理商： MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
10
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
H_NMI
OD
VDD2.5
Non-Maskable Interrupt. H_NMI is used to force a non-maskable interrupt
to the processor. Enabled through I/O 70h bit 7. May be driven by the fol-
lowing assuming that it is enabled: LPC error, LPC transaction timeout,
SERR#, PERR#, IOCHK# off of the L_SERIRQ, or by writing bit 23 of Function
0 Register 44h. H_NMI requires an external weak pull-up to ensure a high
level to the processor.
H_SLEEP#
OD
VDD2.5
Processor Sleep. This signal puts the processor into a state that saves sub-
stantial power compared to Stop-Grant state. However, during that time,
no snoops occur. The I/O Controller can optionally assert H_SLEEP# signal
when going to the S1 state. H_SLEEP requires an external weak pull-up to
ensure a high level to the processor.
H_SMI#
OD
VDD3.3
System Management Interrupt. H_SMI# is an active low output synchro-
nous to PCLK. H_SMI# is asserted by the I/O Controller in response to one
of many enabled hardware or software events. H_SMI# requires an exter-
nal weak pull-up to ensure a high level to the processor.
H_STPCLK#
OD
VDD3.3
Stop Clock Requests. H_STPCLK# is an active low output synchronous to
PCLK. H_STPCLK# is asserted by the I/O Controller in response to one of
many hardware or software events. When the processor samples
H_STPCLK# asserted, it will respond by stopping its internal clock and by
issuing a stop grant cycle. H_STPCLK# requires an external weak pull-up to
ensure a high level to the processor.
KBDRST#
I
VDD3.3
Keyboard Controller Reset Processor. When the I/O Controller detects the
assertion of this signal, H_INIT# is generated for 16 PCI clocks. Note that
the I/O Controller ignores KBDRST# assertion during transitions to the S3,
S4 and S5 states.
Host Interface Signals (continued)
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
PCI Signal Descriptions
SIGNAL
TYPE
POWER
PLANE
DESCRIPTION
P_AD
[31:0]
I/O
VDD3.3
PCI Address and Data are multiplexed on the same pins. A bus transaction
consists of an address phase followed by one or more data phases. The
address is driven when P_FRAME# is asserted and data is driven or received
in the subsequent cycles. When the I/O Controller is acting as the PCI mas-
ter these pins are outputs during the address and write data phases, and
inputs during read data phases. If the I/O Controller is the PCI target these
pins are inputs during the address and write phase, and outputs during the
read phase.
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