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參數(shù)資料
| 型號(hào)： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁(yè)數(shù)： | 66/145頁(yè) |
| 文件大?。?/td> | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
27
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
4
DMA Controller Enable. When set, the DMA core logic is enabled.
When clear, the DMA core logic is disabled and inaccessible.
R/W
0
3
Programmable Interval Timer Enable. When set, the PIT core logic is
enabled. When clear, the PIT core logic is disabled and inaccessible.
R/W
0
2
Legacy Alias Enable. When set, addresses are decoded using ISA legacy
I/O aliasing. When clear, no I/O aliasing is performed during address
decode.
R/W
0
1
Subtractive Decode Enable. When set, all memory and I/O cycles on the
PCI bus that go unclaimed will be subtractively decoded and forwarded
to the LPC bus. When clear, the cycles will be allowed to master-abort.
R/W
1
0
South Core Enable. When set, decode of I/O registers B2h, B3h, 92h,
CF9h is enabled. When clear, decode of these registers is disabled.
R/W
1
Core Bus Control (Device 7h, Function 0h) (continued)
ADDRESS: 40h-43h
SYMBOL: BUS_CTRL
BITS
DESCRIPTION
PROPERTIES
RESET
LPC Long Count Abort Register (Device 7h, Function 0h)
ADDRESS: 44h-47h
SYMBOL: LPCABORT
BITS
DESCRIPTION
PROPERTIES
RESET
31:24
Reserved.
R/O
0
23
Force NMI. Writing a one to this field will force a delayed timeout NMI
and sets status bit when the Delayed Timeout NMI Enable is set.
W/O
0
22:21
Reserved.
R/O
0
20
Delayed Timeout NMI Enable. When set a Delayed Timeout Status from
the LPC bus will cause a NMI. When clear, they have no affect.
R/W
0
19:18
LPC Error Control, including the LPC Delayed Timeout Condition. This
field determines what type of system interrupt is generated when an LPC
error occurs. Allowable values are:
00: NMI
10: SMI
01: SCI
11: Disabled
R/W
0
17
LPC Error status. Set when an LPC error sync has occurred.
R/WOTC
0
16
Delayed Timeout Status. Set when a delayed transaction timeout has
occurred on a cycle from the LPC bus.
R/WOTC
0
15:0
LPC long sync abort count. The number of clocks that an LPC device can
signal a long sync before the LPC bridge aborts the transfer.
R/W
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8LLN22NCNE-A | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET - Trays |
| MT8LLN22NCNE-A2 | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET AND MOTHERBOARD - Trays |
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| MT8LSDT1664AG-10EB1 | 制造商:Micron Technology Inc 功能描述:DRAM MOD SDRAM 1GBIT 168UDIMM - Trays |
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