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參數(shù)資料
| 型號(hào)： | MT8LLN22NCNE |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁(yè)數(shù)： | 74/145頁(yè) |
| 文件大小： | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
34
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Trap Address (Device 7h, Function 0h)
Trap Data (Device 7h, Function 0h)
PCI INT[0] Interrupt Routing (Device 7h, Function 0h)
PCI INT[1] Interrupt Routing (Device 7h, Function 0h)
ADDRESS: 70h-73h
SYMBOL: TRAP_ADDR
BITS
DESCRIPTION
PROPERTIES
RESET
31:0
Address Trapped by SMI or general-purpose trap. For an enabled trap,
this is the address that was present on the PCI bus.
R/W
0
ADDRESS: 74h-77h
SYMBOL: TRAP_DATA
BITS
DESCRIPTION
PROPERTIES
RESET
31:0
Data Trapped by SMI or general-purpose trap. For an enabled trap, this is
the data that was present on the PCI bus. This field is ignored if function
0, register 78h bit 9 is set.
R/W
0
Trap Command (Device 7h, Function 0h)
ADDRESS: 78h-79h
SYMBOL: TRAP_CMD
BITS
DESCRIPTION
PROPERTIES
RESET
15:10
Reserved
R/O
0
9
Enable SMI Trap to be a retry. When set with SMI trap and an enabled
trap, the result of the south bridge trapping the access will be a retry
with an SMI driven to the processor if enabled.
R/W
0
8
Enable SMI Trap. When set the south bridge will drive SMI for an enabled
trap and will fast decode the transaction and provide a response. The
address, data, byte enables, and command for the transaction will be
stored in TRAP_ADDR, TRAP_DATA, and TRAP_CMND. The following reg-
isters define enabled traps: DEVSTS, DEVCTL, GPAR1, and GPAR0.
R/W
0
7:4
BE Trapped for SMI or general-purpose trap. For an enabled trap, this is
the byte enable field that was present on the PCI bus.
R/W
0
3:0
Command Trapped for SMI or general-purpose trap. For an enabled trap,
this is the command field that was present on the PCI bus.
R/W
0
ADDRESS: 80h
SYMBOL: PCI_INT0
BITS
DESCRIPTION
PROPERTIES
RESET
7:0
See register description for “PCI INT[A] Interrupt Routing (Device 7h,
R/W
80h
ADDRESS: 81h
SYMBOL: PCI_INT1
BITS
DESCRIPTION
PROPERTIES
RESET
7:0
See register description for “PCI INT[A] Interrupt Routing (Device 7h,
R/W
80h
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT8LLN22NCNE-A | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET - Trays |
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