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參數(shù)資料
| 型號(hào)： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁(yè)數(shù)： | 142/145頁(yè) |
| 文件大?。?/td> | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
96
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
NOTE:
Register is standby powered and unaffected by SB_POWEROK or P_RST#. Reset only with RSMRST#.
Scratch Pad
NOTE:
Register is standby powered and unaffected by SB_POWEROK or P_RST#. Reset only with RSMRST#.
6
THRM_OVR_EN. Thermal Override Enable. When set, the corresponding
event in the GPSTS0 register will cause a SCI, SMI#, or wake event. When
clear, SCI, SMI#, or wake event will be generated.
R/W
0
5
THRM_EN. Thermal Enable. When set, the corresponding event in the
GPSTS0 register will cause a SCI, SMI#, or wake event. When clear, no SCI,
SMI#, or wake event will be generated.
R/W
0
4
Micron Reserved.
R/W
0
3
USB_EN. USB Enable. When set, the corresponding event in the GPSTS0
register will cause a SCI, SMI#, or wake event. When clear, no SCI, SMI#,
or wake event will be generated.
R/W
0
2
SMB_EN. SMB Enable. When set, the corresponding event in the GPSTS0
register will cause a SCI, SMI#, or wake event. When clear, no SCI, SMI#,
or wake event will be generated.
R/W
0
1
EXT_SMI_EN. External SMI Enable. When set, the corresponding event in
the GPSTS0 register will cause a SCI, SMI#, or wake event. When clear, no
SCI, SMI#, or wake event will be generated.
R/W
0
PME_EN. PME Enable. When set, the corresponding event in the GPSTS0
register will cause a SCI, SMI#, or wake event. When clear, no SCI, SMI#,
or wake event will be generated.
R/W
0
ADDRESS: ACPI_BASE + 18h
SYMBOL: SCRATCH
BITS
DESCRIPTION
PROPERTIES
RESET
31:0
This register may be used as scratch pad.
R/W
0
USB Capabilities Control
ADDRESS: ACPI_BASE + 1Ch
SYMBOL: USB_CAP
BITS
DESCRIPTION
PROPERTIES
RESET
31:12
Reserved.
R/W
0
11
Map USB_STS to PME_STS bit. Setting this bit will have an enabled USB
event to set the PME_STS bit in GPSTS0.
R/W
0
10
Ignore OHCI enables for USB_STS generation. When set the Port Enable
Status, Low Speed Device Attached, and Device Remote Wakeup Enable
from OHCI will be ignored in the generation of USB_STS.
R/W
0
9
Ignore OHCI status flags for USB_STS generation. When set the Current-
ConnectStatus and PortSuspendStatus from OHCI will be ignored in the
generation of USB_STS.
R/W
0
8:7
Reserved.
R/W
0
General Purpose 0 Enable (continued)
ADDRESS: ACPI_BASE + 16h
SYMBOL: GPEN0
BITS
DESCRIPTION
PROPERTIES
RESET
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8LLN22NCNE-A | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET - Trays |
| MT8LLN22NCNE-A2 | 制造商:Micron Technology Inc 功能描述:COPPERTAIL CHIPSET AND MOTHERBOARD - Trays |
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| MT8LSDT1664AG-10EB1 | 制造商:Micron Technology Inc 功能描述:DRAM MOD SDRAM 1GBIT 168UDIMM - Trays |
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