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參數(shù)資料
| 型號(hào)： | MT8LLN22NCNE |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁(yè)數(shù)： | 117/145頁(yè) |
| 文件大小： | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
73
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
DMA Status Register
3Reserved.
W/O
0
2
DMA Controller Enable. When set, the DMA channel group is disabled.
When clear, the DMA channel group is enabled. DMA1 is cascaded into
DMA2 (channel 4) and that disabling DMA2 will consequently disable
DMA1.
W/O
0
1:0
Reserved.
W/O
00
ADDRESS: 08h
SYMBOL: DMASTS
ADDRESS: D0h
DMA1
DMA2
BITS
DESCRIPTION
PROPERTIES
RESET
7:4
DMA Channel Request Status. When set, indicates that a hardware or
software channel request has been made. DMA1 is cascaded into DMA2
through channel 4, so the request status of channel 4 is a logical OR of
the request status for channels 0-3.
Bit 7: Channel 3/7
Bit 6: Channel 2/6
Bit 5: Channel 1/5
Bit 4: Channel 0
R/O
0
3:0
DMA Channel Terminal Count Status. When set, indicates that the termi-
nal count has been reached for the channel. Channel 4 is programmed
for cascade, so the terminal count of channel 4 is not relevant.
Bit 7: Channel 3/7
Bit 6: Channel 2/6
Bit 5: Channel 1/5
Bit 4: Channel 0
R/O
0
DMA Command Register (continued)
ADDRESS: 08h
SYMBOL: DMACMD
ADDRESS: D0h
DMA1
DMA2
BITS
DESCRIPTION
PROPERTIES
RESET
DMA Write Single Mask
ADDRESS: 0Ah
SYMBOL: DMA_WRMSK
ADDRESS: D4h
DMA1
DMA2
BITS
DESCRIPTION
PROPERTIES
RESET
7:3
Reserved.
R/O
00000
2
Mask status update. When set, the mask bit is set. When clear, the mask
bit is clear.
A reset will set all mask bits, disabling all channels. Note that masking
Channel 4 requests will result in masking off all of DMA1’s channels (0:3).
A channel’s mask bit is automatically set when Terminal Count is reached,
unless the channel is programmed for auto-initialization.
W/O
1
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