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參數(shù)資料
| 型號： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 92/144頁 |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_pcix_regs.fm.01
October 15, 2001
Configuration Registers
Page 51 of 144
5.2.4.12 Upper Memory Base Address Register
This register and the memory space defined by it are enabled by the strapping pin, BAR_EN. When the
BAR_EN pin is pulled low, this register location returns zeros for reads and cannot be written. When the
BAR_EN pin is pulled high, the upper memory base address register specifies address bits 63:32 of the 64 bit
memory base address register. Memory accesses on the primary bus are compared against this register, if
address bits 63:20 are equal to bits 63:20 of the address defined by the combination of the lower memory
base address register and the upper memory base address register, the access is claimed by the bridge and
passed through to the secondary bus. Memory accesses on the secondary bus are also compared against
this register, if address bits 63:20 are equal to bits 63:20 of the address defined by the combination of the
lower memory base address register and the upper memory base address register, the access is ignored by
the bridge.
5.2.4.13 Primary Bus Number Register
The Primary Bus Number register is used to record the bus number of the PCI bus segment to which the
primary interface of the bridge is connected. The configuration software programs the value in this register.
The bridge uses this register to decode Type 1 configuration transactions on the secondary interface that
must be converted to special cycle transactions on the primary interface.
Address Offset
x‘14’
Access
See individual fields
Reset Value
x‘0000 0000’
Note: When BAR_EN (pin G2) is tied low this register returns zero and cannot
be written.
Table 7-3 on page 113 for details of strapping considerations.
Upper Memory Base Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
31:0
RW
Upper Memory Base Address
Address bits 63:32 of the base address for an address range of prefetchable memory operations that are
passed from the primary to the secondary PCI bus.
Address Offset
x‘18’
Access
Read/Write
Reset Value
x‘00’
Primary Bus Number
7
6
5
4
3
2
1
0
Bit(s)
Access
FieldNameand Description
7:0
RW
Software sets this register to the bus number of the bus segment that is attached to the primary interface of the
bridge.
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