參數(shù)資料
型號： IBM21P100BGC
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA304
封裝： 31 X 31 MM, PLASTIC, BGA-304
文件頁數(shù)： 16/144頁
文件大小： 5197K
代理商： IBM21P100BGC
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Signal Descriptions
Page 112 of 144
ppb20_signals.fm.01
October 15, 2001
S_PAR
I/O
1
Parity
Parity protection bit for the lower half of the address/data and command/byte enable
buses on the secondary interface. It provides even parity across S_AD(31:00) and
S_C/BE(3:0)#.
S_PAR64
I/O
1
Parity Upper DWord
Parity protection bit for the upper half of the address/data and command/byte enable
buses on the secondary interface. It provides even parity across S_AD(63:32) and
S_C/BE(7:4)#.
S_PERR#
I/O
1
Parity Error
Used to report data parity errors on the secondary interface.
S_PERR# is monitored by the bridge when performing a secondary bus write transaction
on behalf of a primary bus master or when serving as the selected slave for a secondary
bus read transaction.
S_PERR# is driven by the bridge when performing a secondary bus read transaction on
behalf of a primary bus master or when serving as the selected slave during a secondary
bus write transaction.
S_REQ1GNT#
I
1
Request 1
This is a dual-purpose signal:
When the bridge’s internal arbiter is enabled, this signal is used as a request input, to be
activated by a secondary bus master requesting the use of the secondary bus.
When the internal arbiter is disabled, this signal is used by the bridge as its grant input
signal.
S_REQ2# - S_REQ6#
I
5
Requests 2-6
Activated by the secondary bus masters to request the use of the secondary bus.
S_REQ64#
I/O
1
Request 64-Bit Transfer
This signal, when asserted by the current master on the secondary bus, indicates a
desire to transfer data using 64 bits.
S_RST#
O
1
Secondary Bus Reset
S_RST#, driven by the bridge, is the secondary bus reset signal.
Asserted when P_RST# is active or when the secondary bus reset bit in the bridge con-
trol register is set.
S_SERR#
I
1
System Error
Used to report address parity errors and other system errors where the results will be
catastrophic.
S_SERR# is monitored by the bridge to detect these errors on the secondary bus. When
S_SERR# is asserted, it results in P_SERR# being asserted on the primary bus by the
bridge.
S_STOP#
I/O
1
Stop
Indicates that the current target is requesting that the initiator stop the current transac-
tion on the secondary bus.
S_STOP# is monitored by the bridge when performing a secondary bus transaction on
behalf of a primary pus master.
S_STOP# is driven by the bridge when addressed as a target and is asserted low to indi-
cate target termination.
S_TRDY#
I/O
1
Target Ready
Indicates the ability of the target on the secondary bus to complete the current data
phase of the transaction. It is used in conjunction with the S_IRDY# signal.
S_TRDY# is monitored by the bridge when performing a secondary bus transaction on
behalf of a primary bus master.
S_TRDY# is driven by the bridge when a secondary bus master is performing a transac-
tion in which the bridge is the selected target.
Total
98
Table 7-2. Secondary Interface Signal List (Page2of 2)
Signal Name
I/O
Width
Description
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