IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_pcix_regs.fm.01
October 15, 2001
Configuration Registers
5.2.4.4 Status Register
This register records the status of PCI events.
Address Offset
x‘06’
Access
See individual bit fields. Reads to this register behave normally. Writes are
slightly different in that bits can be reset, but not set. A bit is reset whenever the
register is written, and the data in the corresponding bit location is a ‘1’.
Reset Value
x‘02B0’ in the PCI mode, x‘0230’ in the PCI-X mode
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15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
15
RW
Detected Parity Error Status
0
Device did not detect a parity error.
1
Device detected a parity error.
14
RW
Signaled System Error Status
0
Device did not generate a SERR# signal.
1
Device generated a SERR# signal.
13
RW
Received Master Abort Status
0
Bus master transaction was not terminated with a bus master abort.
1
Bus master transaction terminated with bus master abort.
12
RW
Received Target Abort Status
0
Bus master transaction was not terminated by a target abort.
1
Bus master transaction terminated by a target abort.
11
RW
Signaled Target Abort Status
0
Target device did not terminate a transaction with a target abort.
1
Target device terminated a transaction with a target abort.
10:9
RO
Device Select (DEVSEL) Timing Status
01
Medium.
8
RW
Data Parity Status
0
No data parity errors encountered.
1
Data parity errors encountered (this bit for bus masters only).
7
RO
Fast Back-to-Back Status
0
Target not capable of accepting fast back-to-back transactions in the PCI-X mode.
1
Target capable of accepting fast back-to-back transactions in the conventional PCI mode.
This bit is set by hardware when the primary interface is in the PCI mode and is set to a b‘0’ when the primary
interface is in the PCI-X mode.
6
RO
Reserved