參數(shù)資料
型號： IBM21P100BGC
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA304
封裝： 31 X 31 MM, PLASTIC, BGA-304
文件頁數(shù)： 12/144頁
文件大小： 5197K
代理商： IBM21P100BGC
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_signals.fm.01
October 15, 2001
Signal Descriptions
Page 109 of 144
7. Signal Descriptions
This section describes in detail each input and output signal of the IBM 133 PCI-X Bridge R2.0. Throughout
this section, trailing pound signs, for example P_ACK64#, designate signals that are active low.
7.1 Primary Interface Signals
Table 7-1. Primary Interface Signal List (Page1of 2)
Signal Name
I/O
Width
Description
P_ACK64#
I/O
1
Acknowledge 64-Bit Transfer
Asserted by the currently addressed target on the primary bus to indicate its willingness
to transfer data using 64 bits.
P_AD(63:00)
I/O
64
Multiplexed Address and Data
64-bit multiplexed address and data bus, shared by other devices on the primary bus.
During a transaction, this bus contains the physical bus address, attributes, or data, or it
may be reserved.
P_C/BE(7:0)#
I/O
8
Multiplexed Bus Command and Byte Enables
During a transaction, these eight bits define the bus command, attributes, or byte
enables for the transfer. These signals are shared with other agents on the primary bus
and at times may be reserved.
P_CLK
I
1
Clock
Received by the bridge and provides timing for all operations on the primary interface.
P_DEVSEL#
I/O
1
Device Select
Asserted by the target on the primary bus that decoded the address of the current trans-
action as being within one of its address ranges.
P_DEVSEL# is monitored by the bridge when performing a primary bus transaction on
behalf of a secondary bus master.
P_DEVSEL# is driven by the bridge when a primary bus master is performing a transac-
tion on the primary bus intended for a secondary bus slave or the bridge's configuration
registers.
P_FRAME#
I/O
1
Cycle Frame
Defines the beginning and duration of each primary bus transaction and is controlled by
the initiator of the operation.
P_FRAME# is driven by the bridge when performing a primary bus transaction on behalf
of a secondary bus master.
P_FRAME# is monitored by the bridge when a primary bus master is performing a trans-
action on the primary bus.
P_GNT#
I
1
Grant
Indicates that the bridge has been granted access to the primary bus.
P_IDSEL
I
1
Initialization Device Select
Used as a chip select during configuration read and write transactions on the primary
bus.
P_IRDY#
I/O
1
Initiator Ready
Indicates the ability of the initiator on the primary bus to complete the current data phase
of the transaction. It is used in conjunction with P_TRDY#.
P_IRDY# is driven by the bridge when performing a primary bus transaction on behalf of
a secondary bus master.
P_IRDY# is monitored by the bridge when a primary bus master is performing a transac-
tion on the primary bus to or through the bridge.
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