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參數(shù)資料
| 型號(hào)： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 4/144頁 |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_clock_reset.fm.01
October 15, 2001
Clocking and Reset
Page 101 of 144
Since the internal PLL is bypassed in the PCI mode and the S_CLK input is used directly, the IBM 133 PCI-X
Bridge R2.0 has no need to distinguish between the PCI 66 and PCI 33 modes. Therefore the bridge does not
have an I/O pin for the M66EN signal on its secondary interface. This signal should be routed to all devices on
the bus in case the other clients require it.
6.4 Clock Stability
The PCI/PCI-X architectures specify that the bus clock must be stable and running at its designated
frequency for at least 100
s prior to the de-assertion of the bus reset signal. As the IBM 133 PCI-X Bridge
R2.0 does not generate the secondary bus clock but does control the secondary bus reset signal, it must
detect when the S_CLK input has become stable in order to meet this requirement. The input signal
S_CLK_STABLE is provided for this purpose. During a bus reset, the bridge will wait for the assertion of the
S_CLK_STABLE input before executing the mode and frequency determination sequence described in
The bridge is expecting at most one transition on the S_CLK_STABLE input from the not stable to the stable
state. The S_CLK_STABLE input may also be tied-up if the secondary clock input will always be stable prior
to the de-assertion of the primary bus reset signal or the secondary bus reset bit of the bridge control register
(see
Section 6.6.2 on page 103).There are several possibilities for the source of the S_CLK_STABLE input
signal. For example: some clock generation circuits that use phase-locked loops provide a lock indicator that
may be used for this purpose. Care must be taken to assure that the lock indicator does not toggle randomly
while the PLL is locking to the desired frequency before reaching a steady state. Another possibility is to
Figure 6-1. Programmable Pull-up Circuit
3.3V
S_PCIXCAP
S_PCIXCAP_PU
Weak
Pull-up
Strong
Pull-up
For PCI-X
66 MHz Cards
For PCI-X
100/133 MHz Cards
For PCI
Cards
S_SEL100
3.3V
For 100 MHz
For 133 MHz
Enabled During
Bus Capability
Determination
IBM 133 PCI-X Bridge R2.0
10k
0.01mF
56k
10k
1k
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