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| 型號(hào)： | IBM21P100BGC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封裝： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 10/144頁(yè) |
| 文件大?。?/td> | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_clock_reset.fm.01
October 15, 2001
Clocking and Reset
Page 107 of 144
Applications that require access to the bridge configuration registers via the secondary bus may optionally
control the initialization sequence through the P_CFG_BUSY pin and bit 2 of the miscellaneous control
register. When P_CFG_BUSY is pulled high, bit 2 of the miscellaneous control register is set to b'1' at power
up and reset. This causes the bridge to retry Type 0 configuration transactions on the primary bus that would
otherwise be accepted. The bridge continues to retry these transactions until such time as bit 2 of the miscel-
laneous control register is set to b'0' by a configuration write initiated on the secondary bus. This mechanism
allows an agent on the secondary bus to initialize the bridge and any private devices on the secondary bus
without contention from agents accessing the bridge via the primary bus.
Applications that do not require access to the bridge configuration registers via the secondary bus should pull
both the S_IDSEL and P_CFG_BUSY pins low.
6.13 Short Term Caching
Short Term Caching was developed to provide performance improvements where upstream devices are not
able to stream data continuously to meet the prefetching needs of the IBM 133 PCI-X Bridge. As defined in
the
PCI to PCI Bridge Architecture Specification, when the master completes the transaction, the bridge is
required to discard the balance of any data that was prefetched for the master. To prevent performance
impacts when dealing with target devices that can only stream data of from 128 to 512 bytes before discon-
necting, the IBM 133 PCI-X Bridge has a feature called “Short Term Caching”. This feature applies only when
the secondary bus is operating in PCI mode and provides a time limited read data cache in which the bridge
will not discard prefetched read data after the request has been completed on the initiating bus.
Short Term Caching is an optional feature which is enabled by setting the “Miscellaneous Control Register 2”
bits 8 and 15. When enabled, the IBM 133 PCI-X Bridge will not discard the additional prefetched data when
the read transaction has been completed on the initiating bus. As such, the IBM 133 PCI-X bridge will
continue to prefetch data up to the amount specified by the “Secondary Data Buffering Control Register”
offset x’42’ bits 14:12. Should the initiator generate a new transaction requesting the previously prefetched
data, the IBM 133 PCI-X Bridge will return that data. However, the IBM 133 PCI-X Bridge will discard the data
approximately 64 secondary bus side clocks after some of the data for a request has been returned to the
initiator, and the initiator has not requested additional data.
If this feature is enabled, it will apply to all devices attached to the secondary side of the IBM 133 PCI-X
Bridge. System designers need to ensure that all attached devices have memory region(s) that are archi-
tected to be accessed by only one master and that the additional prefetching will present data to the initiator
in the same state as if the initial transaction were continued. This feature should only be used in system
designs that are able to ensure that the data provided to the master has not been modified since the initial
transaction.
Note: A clear understanding of all the secondary side device’s device drivers and memory architectures, and
ensuring that the PCI to PCI Bridge Architecture Specification as stated in Chapter 5, sections 5.1
Prefetching
Read Data and 5.6.2 Stale Data has been strongly adhered to, is required to prevent stale data from being
delivered to the master.
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